Ok, I am "basement builder." I am almost done building a clock(a very common project).
Now, I wanted to understand more about the chip 74LS90 itself.
So, the chip has two AND gates (pin2,3=reset 0, pin6,7=reset 9).
The chip can count anything from 2 to 10 by connecting the appropriate output pins(QA,B,C,D) to the pins 2,3 to get a count from 0 to X.
So, for example, If I connected QB,QC to pin 2,3 , then I would get a modulo 6 count. That's because 6 in binary is 110. so B,C would be logic1 then, causing the pin2,3 AND gate to have output=1 , therefore resetting the counter to 0.
Here is my "question." Why do I see many designs that have external AND gates for doing the same thing rather than using the internal AND gate? Is there something else I am not seeing?
Now, I wanted to understand more about the chip 74LS90 itself.
So, the chip has two AND gates (pin2,3=reset 0, pin6,7=reset 9).
The chip can count anything from 2 to 10 by connecting the appropriate output pins(QA,B,C,D) to the pins 2,3 to get a count from 0 to X.
So, for example, If I connected QB,QC to pin 2,3 , then I would get a modulo 6 count. That's because 6 in binary is 110. so B,C would be logic1 then, causing the pin2,3 AND gate to have output=1 , therefore resetting the counter to 0.
Here is my "question." Why do I see many designs that have external AND gates for doing the same thing rather than using the internal AND gate? Is there something else I am not seeing?