1-5 second delay-on circ, using 100k pot

was wondering if someone could post a circuit schematic. with the correct values using a 100k potentiometer to adjust the delay from 1-5 seconds. the circuit is cmos so everything is 5v so the circuit is such..... using a sr latch, the set output goes the the timer circuit, delaying the 5v output for 1-5 seconds, that 5v goes into a cmos buffer IC. I only would like the timer schematic with correct values of capacitor and resistors. I do not want to use a ne555 or crystal..... just a simple capacitor and bias resistors.. it is not critical, timing close to 1 second and close to 5 seconds is good enough... I started a different post trying to use my existing circuit, but now , thinking it may be best to use the correct values to get the desired range. as my current configuration goes from 0 seconds to many hours.... which I dont need. my other post was heading in this direction, so I thought to keep the subject matter correct, a new post was in order, thanks again, Steve
 
Look at figures 6-1 to 6-15 in this reference. Which type of delay do you want? Edge-triggered or Pulse triggered? Rising edge, falling edge? Level triggered (where the triggering signal is longer than 5 sec) or pulse triggered (where the pulse is shorter than the output)?
 
I think you misunderstood my need...... I do not require a pulse. to simplify, If I were using a toggle switch, I would throw the switch then 1-5 seconds later the power would come on. depending on the position of the pot. I am not using a toggle switch, I am using a sr latch to provide the 5v that a toggle switch would provide, which then after a 1-5 second delay, that 5v produced by the delay circuit will go through a cd4050 buffer/line driver. its an on delay.......
I am going to look trough the information though, as it is very informative......
 

How long is the flip-flop off before the next time it is turned back on?

How much current do you draw from the timer's output?
 
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More than 5 seconds, a few minutes probly.

The current draw is not an issue

The current is minimal it drives a cmos buffer cd4050

I have been looking on google and came across the formula T=RC, I am locked into using a 100k pot, or a 10k pot. whichever is better. I would like to only have the range between 1-5 seconds, my confusion is how to only stay within that range. I assume I will need to put a resistor in series with the pot. also dont know the exact draw the cd4050 draws, and if I need to use a pull down resistor, and if that changes all of the values..... I don't use formulas, I usually breadboard test things to get the values, whichsometimes things are not balanced very well..... and It takes a long time...... I guess a Lab guy....not so much math and formulas....... thats why I am asking.....
 
Try this:

Not ideal, the delays will only be approximate. You would do better with a CMOS Schmitt input gate or buffer, or with a 555, which has more reliable trip points.

The signal Q (upper plot pane) is what comes from your flip-flop. In the sim, it goes high at 1s, and stays high until 9s.

The output from the 4050 buffer goes high at 2s (green), ~4s (red) or ~6s (blue) as the pot resistance goes from 0Ω, 50KΩ and 100K, which is a delay of 1s, ~3s, and ~5s, respectively.

You will be lucky to get timings of +-20% as the input trip point of the 4050 is not very well controlled.
 

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would a 1n5817 diode (schottky) work ok, seeing timing isn't critical? what if any negative effect would it have? +-20% is fine, the function the timing controls does not warrant more components..... worst case scenario is It would take an extra 30 seconds out of my day..... I need to order some stuff then will try It out ..... thanks...... Steve
 
A 1n5817 will work a little better than a 1n914, but costs more. If you already have some, ....
 
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