100uF Ceramics - Capacitance at higher voltage

[Tony Stewart]

ok your requirements are a bit clearer.

1. with 100Hz rectified must hold up above minimum input voltage so output does not drop but with 0.12V drop or 2.4% of 5V regulated , may assume input dropped from 8.4Vdc
2. any design that needs needs 10% ripple of unregulated input needs RC=~5T for T=rectified cycle of 10ms, then C=~5*10ms/5Ohm= 10mF. if your C is smaller then possibly input ripple Vpp is greater.
3. When pumping a limited current at low ripple into caps, the ESR produces a step voltage while charging up the C with a triangular wave on top.
4. minimizing ESR by choice of 1 best cap or two or three different types is historically done like 100uF, 1uF, 0.01uF, so that when SRF is exceeded in the biggest cap , it turns inductive then the next smaller cap shunts this in parallel as f rises and so forth. (simplistic view)
5. Ceramic caps can work well under good layout, soldering , bias and temp restrictions. Chosen poorly, results,are same.
6. Plastic caps are far more ideal electrically, but low density makes them suitable for lower C higher RF, higher V, higher ripple current.
7. Examine the specs of the Murata cap chosen for output and the layout.. Loop area from switcher to output cap Must be kept low for any cap >=50KHz as impedance from trace inductance rises with harmonic f of pulses and base switching rate.
8. Inductor must also be low ESR and small value like the demo board which uses 22uH and 1uH , NOT mH !

 

[ronsimpson]

I couldn't find any data for the 100uF cap though, or any for that series, where does it say 'Z' is high @ 340KHz?

Here is data from TDK: 100uF 25V
This cap resonates at 500khz and probably should not be tested at that frequency.
I have good data from TDK.

 

[Tony Stewart]

Here is data from TDK: 100uF 25V
This cap resonates at 500khz and probably should not be tested at that frequency.
I have good data from TDK.
[]

Looks good. too bad, not in stock.

**broken link removed**

fyi

 

[ronsimpson]

What size are you looking for? English or Metric

 

[Tony Stewart]

i think 1206 ...3225 metric

 

[Tony Stewart]

If you should wish to design a DC-DC in future .. cosult TI or LT website.. All the work is automated for any custom design in a limited range of simple power supplies, with all the necessary details for a design.

https://webench.ti.com/WebenchRepor...panyName=’TI’&wb5_navbar_design=1362527186704

 

[KeepItSimpleStupid]

ESR: Take a look here: https://en.wikipedia.org/wiki/Electrolytic_capacitor under Series Equivalent Circuit.

 

[ACharnley]

ok your requirements are a bit clearer.

1. with 100Hz rectified must hold up above minimum input voltage so output does not drop but with 0.12V drop or 2.4% of 5V regulated , may assume input dropped from 8.4Vdc
2. any design that needs needs 10% ripple of unregulated input needs RC=~5T for T=rectified cycle of 10ms, then C=~5*10ms/5Ohm= 10mF. if your C is smaller then possibly input ripple Vpp is greater.
3. When pumping a limited current at low ripple into caps, the ESR produces a step voltage while charging up the C with a triangular wave on top.
4. minimizing ESR by choice of 1 best cap or two or three different types is historically done like 100uF, 1uF, 0.01uF, so that when SRF is exceeded in the biggest cap , it turns inductive then the next smaller cap shunts this in parallel as f rises and so forth. (simplistic view)
5. Ceramic caps can work well under good layout, soldering , bias and temp restrictions. Chosen poorly, results,are same.
6. Plastic caps are far more ideal electrically, but low density makes them suitable for lower C higher RF, higher V, higher ripple current.
7. Examine the specs of the Murata cap chosen for output and the layout.. Loop area from switcher to output cap Must be kept low for any cap >=50KHz as impedance from trace inductance rises with harmonic f of pulses and base switching rate.
8. Inductor must also be low ESR and small value like the demo board which uses 22uH and 1uH , NOT mH !

4. I have something like this already, there's a 10uF 25v ceramic in parallel.
8. Sorry 15uH!

The graph you have for the 100uF 25v isn't the same model but I assume it's close. I believe my understanding of SRF and it's importance is clearer, essentially the capacitor has some inductance and acts as a filter, if the frequency is close it passes it through and it's ability to charge will be impaired. I guess it'll cause the capacitor to heat as well.

 

[ACharnley]

So solution time...

I know from the electrolytic that I need 330uF to ensure stability. I can get away with less in real world say 220uF.

The electrolytic is too big for the case (as is a 25v 47uf). Sticking it outside will require a wire (possible ESR problem there) and will be ugly. Also long term reliability needs to be high.

The ceramics are tiny and fit well but have the SRF close to the buck switch frequency. Thinking out loud, how about two in series = 50uF x 4 in parallel?

Tantalum 25v 100uF can fit as well (7843) but probably only two. Depending on who you talk to some say avoid.

Remember normal working voltage is 8.4v, max is 20v. At 20v there will be little current consumption and as soon as a load is placed this voltage will drop quickly. In other words the capacitors can expect to work hard at 8.4v.

I have 6,000 TDK caps (it would be good to use them up if there's a method!).

 

[ACharnley]

Another option, I can get 25v 47uF 1206 Y5V ceramics very cheap ($0.03). I've requested the data sheet to see if they'll work and will report back.

Here's another option

TDK 47uF 25v C3216X5R1E476M160AC $0.08/pcs

https://product.tdk.com/en/search/capacitor/ceramic/mlcc/info?part_no=C3216X5R1E476M160AC

 

[ACharnley]

C3216X5R1E476M160AC data

Capacitance - frequency is ok.

ESR, ESL - very good at 380khz.

Previously I thought low impedance had to be avoided, but it's still 2Mohm at the lowest point? Wasn't that the issue with the 100uF? Still confused I reckon!

 

[spec]

This data may be of interest:

(1) Tantalum Capacitors
Tantalum capacitors should only be used where the current is limited or they will fail.

(2) Metal Film Capacitors
The major disadvantage of metal film capacitors is that they are physically large for a given capacitance and working voltage. They are also relatively expensive. Also the best metal film capacitor, polycarbonate, is no longer available because the dialectic film is no longer manufactured.

Polypropylene metal film capacitors, which have a good electrical performance, are not available in surface mount because they cannot stand the temperature of surface mount soldering.

Polyester metal film capacitors are cheap but do not have the best electrical characteristics.

Polyphenylene sulfide metal film capacitors have a good electrical performance, good temperature, and low cost.

(3) Ceramic Capacitors
As a general rule, taking X7R dialectic, the physically smaller the ceramic capacitor is, for a given value, the worse the temperature and voltage variation. For this reason, when you calculate worst case tolerance, you may find that a particular ceramic capacitor is unsuitable for a particular application when at first sight it seems ideal because of its small size low ESR and high resonant frequency. It does not help either that ceramic capacitors suffer from the piezoelectric effect.

(4) Links and edocs

https://en.wikipedia.org/wiki/Ceramic_capacitor

 

[Tony Stewart]

C3216X5R1E476M160AC data

Capacitance - frequency is ok.

ESR, ESL - very good at 380khz.

Previously I thought low impedance had to be avoided, but it's still 2Mohm at the lowest point? Wasn't that the issue with the 100uF? Still confused I reckon!

The only thing confusing to me are your priorities and overall measureable objectives. Cost, Qty, performance. Your design is far from complete or ideal,but may work in some conditions.

-low ESR means less loss or to dissipate less heat. (good) but if no current limit elsewhere can conduct more current...which needs attention.

-reactive impedance stores energy or changes impedance with f or Z(f)

-when you operate past SRF, phase of current shifts with voltage 180 deg and closed loop can become unstable, unless shunted with another part to take over.

 

[ACharnley]

Hi Tony,

You must understand I am human lacking any sort of qualification in this stuff. To understand these attributes I need a picture in my head, a context - throwing "voltage 180 deg and closed loop" at me wont help!

I'm reading this and beginning to consolidate my understanding, I assumed for the graph Z the lower point was better when it's the inverse. Hence when you said 500Hz is close to the SRF there is a lack of capacitance. Now it makes sense. On this resource there's also a comparison with an equal electrolytic which shows how the SRF is much higher. https://www.murata.com/en-eu/products/emiconfun/capacitor/2013/02/14/en-20130214-p3. This matches what I'm seeing under lab testing.

My overall objective is performance (today and long term, in 10-25 years time, hence electrolytic avoidance) within minimal space constraints (hence electrolytic avoidance!). Cost is a distant second. I already have 1,000 built PCB's and they work very well in application. It is only when lab testing with mains frequency that this high voltage drop at high load becomes apparent. During application testing (200Hz AC) there is no problem at all.

Andrew

 

[Tony Stewart]

Hi Tony,

You must understand I am human lacking any sort of qualification in this stuff. To understand these attributes I need a picture in my head, a context - throwing "voltage 180 deg and closed loop" at me wont help!

I'm reading this and beginning to consolidate my understanding, I assumed for the graph Z the lower point was better when it's the inverse. Hence when you said 500Hz is close to the SRF there is a lack of capacitance. Now it makes sense. On this resource there's also a comparison with an equal electrolytic which shows how the SRF is much higher. https://www.murata.com/en-eu/products/emiconfun/capacitor/2013/02/14/en-20130214-p3. This matches what I'm seeing under lab testing.

My overall objective is performance (today and long term, in 10-25 years time, hence electrolytic avoidance) within minimal space constraints (hence electrolytic avoidance!). Cost is a distant second. I already have 1,000 built PCB's and they work very well in application. It is only when lab testing with mains frequency that this high voltage drop at high load becomes apparent. During application testing (200Hz AC) there is no problem at all.

Andrew

Keep in mind the cost of field failures and value of learning from expert designs such as on good motherboards which use solid electrolytics in the DC-DC converters around the CPU. Be aware that ceramic may crack and fail if the PCB bends more than a few degree depending on orientation.

PSU's appear to be very simply, but can have complex failure modes. Better to recognize what makes a PSU reliable and learn from the experts who can demomstrate MTBF like OKI/Murata/Lambda/Rohm than make until you have enough experience. Make /buy and field repair risks always have mathematical solutions with valid assumptions.

Understanding the datasheet and principles that I have injected are essential to starting with a reliable desigsn, then verifying your assumptions with tests.. Like any good design.... Specs then DVT

It akes a lot of experince to make power converters look simple AND reliable AND cheap and best performance AND efficient.. The Texas Instrument (TI) site has the automated design tools on their home page.

 

[ACharnley]

Ok, but getting back on topic, I have two choices (do you agree?); ditch the ceramics completely or use multiple smaller capacitance values, which tend to have higher SRF. Even then, the actual capacitance will be reduced due to the SRF being lower than the equivalent electrolytic which will hence require double or triple the amount to get the same capacitance at 380khz.

PS) PCB's will be encased in titanium and epoxy filled - no chance of flex.

 

[ACharnley]

Ok here it is, I sent an email to the guy at TDK who wrote the presentation linked to earlier. He says the maximum capacitance they do at 100uF is 16V. In other words, my capacitors are fake!

 

[Tony Stewart]

Ok here it is, I sent an email to the guy at TDK who wrote the presentation linked to earlier. He says the maximum capacitance they do at 100uF is 16V. In other words, my capacitors are fake!

Did you use an RLC meter at 100kHz biased at 16V? THis uses a constant current sine wave and measures voltage amplitude and phase to compute all the parameters. I doubt you did that.

 

[Tony Stewart]

Ok, but getting back on topic, I have two choices (do you agree?); ditch the ceramics completely or use multiple smaller capacitance values, which tend to have higher SRF. Even then, the actual capacitance will be reduced due to the SRF being lower than the equivalent electrolytic which will hence require double or triple the amount to get the same capacitance at 380khz.

PS) PCB's will be encased in titanium and epoxy filled - no chance of flex.

You need to do the homework I suggested to properly choose the range of possible choices and match that with available parts.
I won't make any more suggestions unless all the parameters for Cap are defined. Ripple current, desired ripple voltage, worst case V-I range, frequency, location on schematic, temperature range - to +, MTBF at worst case internal ambient and max load. Layout, solder method.

 

[ACharnley]

I don't have such a device to hand.

He sent a ton of good information over such as this on measuring high cap ceramics: **broken link removed**

Confirmed capacitors are very much fake. Looking to retrofit tantalum 220uf/25v x2, else the capacitance will have to be stuck outside the case.