I would suggest you get a datasheet for this chip. It has timing diagrams and a shows a typical Shift, load, and inhibit sequence.
In any case, here is what I see is required on a typical parallel load:
1. Clock inhibit (pin 15) high
2. Serial input (Pin 10) low
3. Clock (pin 2) Don't care
4. Data pins a-h; parallel load data
5. Shift load (pin 1) low pulse
When the shift load is pulsed low, data on pins a-h are loaded into the registers provided inhibit is high and serial input is low. If you are NOT chaining these register chips, then suggest you permanently hold the serial input pin low to avoid problems with the parallel load sequence.
Once data is loaded and you want to shift it out serially:
1. Shift load; high
2. clock inhibit; low
3. clock; high pulses
Once the clock inhibit is lowered, the clock lead pulses are used to shift out the data bits from most significant to least significant (h to a)
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