74HC165N PISO Shift Register

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uceesdp

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Hi,

I've got a project that requires the use of a 74165 shift register. However, after countless hours of testing and re-connecting of wires, I don't seem to get it working.

Basically I want, for test purposes, to load 1010 from the parallel input pins and shift it out serially. I have tested it using multisim and sometimes it works but now it does not work watsoever. I've also tried it practically by buying the IC and trying to get the same results, but no luck.

I have attach a schematic that use to work ONLY on multisim.

Thank you
 

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How is the Parallel Load synchronized (or not) with the Count Enable?
 
the PL is not synchronised, it randomly can switch from LOW to HIGH for serially output. Because the clock runs at high freq, it should shift serially anytime. In practical, I used another astable to pulse the PL at very low freq.
 
This will cause uncertainty as to when the output will begin shifting...
 
but because the clk is pulsing at very high frequency there wouldnt be that much of an uncertainty, right?
 
I rearranged the inputs to show which edge causes a change in the output.
 

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Below is my simulation in Electronic Workbench of your circuit, which works as expected.

But, in real life, this circuit could occasionally give an improper output if the load signal is not synchronized to the clock. If the clock and load signal happen to occur at just the right time, the circuit can enter a metastable state where the outputs could be incorrect. If that occasionally happening would be a problem in your application, then you need to synchronize the clock with the load signal using a flip-flop.

 
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Thanks for the response, but it seems to work by putting a high freq clock at dclk pin. Why did the output pin decide to go HIGH prior to PL going LOW?

The only difference in the input pins from mine is that your connected the Ds pic to VCC instead of GND.
 
How would I synchronise the clk with a flip flop? The PL pin for my application is pulsed randomly. IF the clk was pulsed in the MHz region, then the PL pin will probably be in sync.
 

After 7 clocks, the +5V at Ds fills the shift reg with ones, causing Dout to go to One. It goes to Zero aysnchronously with the CLK when the falling edge of PL loads the Zero at D7. The next rising CLK after PL goes High shifts out D6.
 
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uceesdp said:
How would I synchronise the clk with a flip flop? The PL pin for my application is pulsed randomly. IF the clk was pulsed in the MHz region, then the PL pin will probably be in sync.
Click to expand...
You connect the PL signal to the D input and the clock to the clock input of a flip flop. The flip flop Q output goes to a second flip flop D input that is also clocked by your clock (the second flip flop is to minimize the possible metastable problem of the first flip flop). Connect the Q output of the second FF to the PL input of the SR.
 
Thanks guys, I managed to fix the problem with PISO. The problem was the IC itself, it was faulty, I replaced it with a new one and it worked perfectly fine.

A new problem arises.....

The PISO goes into a SIPO with storage (SN74HC594). I can manage to send the serial bits to the sipo and parallel output them with the correct sequence. However, I cannot stop the storage clk in time to display a number.

For example, the piso is clk at high frequency which will also be used for the sipo. After the 4-bit serial data is shifted in the sipo, I want to extract that particular data. So, If i send 0101 (no.5) i want it to appear at the sipo output.

Any suggestions
 
You will need to generate a pulse that occurs 8 clock periods after you start sending the data (SH/LD' goes high), which you use to latch the data into the SIPO output latches. (You can use another shift-register or a counter to generate the 8 clock pulse delay).
 
you mean by letting the serial input to generate 8 counts then on the 8th pulse trigger the storage clk?
 
i tried it, but it does not work. it needs to be triggered on the negative half of the clock, which cannot be done. Your probably thinking use an inverter, but it you try it out, you will see what i mean.
 
Without knowing what your circuit looks like and not being psychic, I can't really understand the problem. What is "it" that needs the negative trigger?
 
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