tech_vaibhav_eee
New Member
Hello,
I am presently working on the design of a 8-bit microprocessor. I am working on my own and dont expect any help from the professors.So, basically my source of knowledge for this project would be internet. I want to keep the project as simple as possible with basic arithmetic and logical instructions and some load/store instructions.
I understand all the digital blocks needed for the design such as memory, register file, ALU, shifters etc. I also understand that the first step needed is to design a datapath and I am working sincerely towards it.
Now, coming to the problems I am facing , I am not being able to understand as to how an indivisual instruction will be executed.
for eg. , suppose I give mov Ax,[Bx] , I need to understand how the hardware executes this instruction.Specific doubts are:
1)Will the whole of the instruction be executed in 1 clock cycle or multiple clock cycles are needed.
2)Should I make the instruction 8 bit or 16bit. Basically , how do I decide the size or the instruction.
3)If the instruction will be 16 bit , only 1st 8 bits will be fetched in the first clock cycle and next 8 bits in the second clock cycle.So, in such a case , how does the hardware executes the instruction.
My opinion: I believe that since my instruction set is small , and since I will be using only one or two addressing modes , 8 bits are enough for a single instruction.
But , at the same time , I feel that the instruction can not be executed in a single clock cycle.
Basically, as you can infer from my my post , I am really confused as to how an indivisual instruction will be executed at the hardware level.
I have a lot more doubts as well but i am not able to express them here.
If someone can explain me the exact working or give me links to materials which can help me, I would be greatful.
Infact , If my approach to the designing of a microprocessor is not correct , I would love if someone could correct me or guide me through this project.
Please , do not ignore this post and help me in any possible capacity
I am presently working on the design of a 8-bit microprocessor. I am working on my own and dont expect any help from the professors.So, basically my source of knowledge for this project would be internet. I want to keep the project as simple as possible with basic arithmetic and logical instructions and some load/store instructions.
I understand all the digital blocks needed for the design such as memory, register file, ALU, shifters etc. I also understand that the first step needed is to design a datapath and I am working sincerely towards it.
Now, coming to the problems I am facing , I am not being able to understand as to how an indivisual instruction will be executed.
for eg. , suppose I give mov Ax,[Bx] , I need to understand how the hardware executes this instruction.Specific doubts are:
1)Will the whole of the instruction be executed in 1 clock cycle or multiple clock cycles are needed.
2)Should I make the instruction 8 bit or 16bit. Basically , how do I decide the size or the instruction.
3)If the instruction will be 16 bit , only 1st 8 bits will be fetched in the first clock cycle and next 8 bits in the second clock cycle.So, in such a case , how does the hardware executes the instruction.
My opinion: I believe that since my instruction set is small , and since I will be using only one or two addressing modes , 8 bits are enough for a single instruction.
But , at the same time , I feel that the instruction can not be executed in a single clock cycle.
Basically, as you can infer from my my post , I am really confused as to how an indivisual instruction will be executed at the hardware level.
I have a lot more doubts as well but i am not able to express them here.
If someone can explain me the exact working or give me links to materials which can help me, I would be greatful.
Infact , If my approach to the designing of a microprocessor is not correct , I would love if someone could correct me or guide me through this project.
Please , do not ignore this post and help me in any possible capacity