AC/DC converter + Totem-Pole

[mading2018]

I think you've proved it's not as simple as you'd like it to be.

Yes, I think so too..

 

[mading2018]

Only one of the PWM circuits in the LT1509 are for PFC control.

I understand that first PWM (GTDR1) is for PFC control. It is also said "totem pole output", so I assume it is specifically for Totem-pole PFC?
In that case I should use LT1509 or LT1508, to connecting to one of the MOSFET. The other MOSFET could maybe be connected with a voltage source with a delay.

Does matter which one I use of LT1509 or LT1508 for my case, cause one of them is a PWM voltage controller and the other one is a PWM current controller.

 

[ChrisP58]

I just to simplify the totem-pole as much as possible. It doesn't need to be complexed.
I need it cause it have a compact design for my charger. My charger is suppose to be so small and lightweight as possible.

Maybe I'm missing something but, all things considered, I don't see the totem pole configuration as being simpler than a conventional PFC.

It may look so at first glance as it uses two mosfets and two diodes, vs. four diodes and one mosfet. But you need to add in an, as yet unknown, different PFC controller, plus the high side mosfet driver. Also, the conventional PFC most likely wouldn't be built with four discrete diodes, but a single full wave bridge. So the comparison is four power semiconductor devices for the totem pole, vs. two power semiconductor devices for the conventional.

 

[ChrisP58]

I understand that first PWM (GTDR1) is for PFC control. It is also said "totem pole output", so I assume it is specifically for Totem-pole PFC?
In that case I should use LT1509 or LT1508, to connecting to one of the MOSFET. The other MOSFET could maybe be connected with a voltage source with a delay.

Does matter which one I use of LT1509 or LT1508 for my case, cause one of them is a PWM voltage controller and the other one is a PWM current controller.

Quoting from the LT1509 datasheet "GTDR1 (Pin 1): The PFC MOSFET gate driver is a fast totem pole output which is clamped at 15V. Capacitive loads like the MOSFET gates may cause overshoot. A gate series resistor of at least 5Ω will prevent the overshoot."
This means that the output circuitry driving the pin itself is a fast totem pole output. Not that it is set up to drive a pair of mosfets in a totem pole configuration. If it were, then the application circuit would have shown that configuration.

 

[mading2018]

Maybe I'm missing something but, all things considered, I don't see the totem pole configuration as being simpler than a conventional PFC

I didn't mean it is simpler than conventional boost PFC. I just want to make the totem-pole simple, if possible.

 

[mading2018]

Quoting from the LT1509 datasheet "GTDR1 (Pin 1): The PFC MOSFET gate driver is a fast totem pole output which is clamped at 15V. Capacitive loads like the MOSFET gates may cause overshoot. A gate series resistor of at least 5Ω will prevent the overshoot."
This means that the output circuitry driving the pin itself is a fast totem pole output. Not that it is set up to drive a pair of mosfets in a totem pole configuration. If it were, then the application circuit would have shown that configuration.

Yes, but I need to improvise a bit cause there is no IC-circuit for totem-pole. Like Ron suggested, could it be possible to use one gate (PFC) and put a delay
to simulate a totem-pole? I have attached my file here, (its not done), but just want to discuss some ideas how it could be done.

 

[ChrisP58]

I didn't mean it is simpler than conventional boost PFC. I just want to make the totem-pole simple, if possible.

But that's where I see the problem. I'm afraid that, regardless of what you may want, driving the totem pole configuration just isn't simple.

Did you notice that on Page 19 of the link you posted, https://www.kivi.nl/uploads/media/59565ab464588/Guido-Schott.pdf, that is says "Only possible with GaN or SiC." While similar to msofets, Galium Nitride and Silicon Carbide devices have different charachteristics. They are not interchangable with conventional mosfets.

 

[ChrisP58]

Yes, but I need to improvise a bit cause there is no IC-circuit for totem-pole. Like Ron suggested, could it be possible to use one gate (PFC) and put a delay
to simulate a totem-pole? I have attached my file here, (its not done), but just want to discuss some ideas how it could be done.

No, because the timing of the second switch does not follow the first by a delay. The timing of the switches in a totem-pole PFC are MUCH more complex that a simple PFC.

Read this. https://www.ti.com/lit/an/slyt718/slyt718.pdf

 

[mading2018]

Yes, I think have some more knowledge how do the switching for totem-pole now, If I could do something similar by implementing the dflipflop with ANDS grinds as you recommended me to do with the interleaved PFC, it may work for the Totem-pole PFC.

--edit--
could i use a BV voltage source to get an delay, and to obtain the same waveforms characteristics for Q1 and Q2? It looks like I need quite a long delay (a halfperiod) before Q2 can start to operating.

 

[mading2018]

I added clock pulses CLK1 and CLK2 to the AND gates to try to get the waveforms characteristics of Q1 and Q2 shown in PNG.file in post #49, but Q1 and Q2 are showing something else. Do anyone have some suggestion how this could be improved?

 

[alec_t]

Your gate drive voltage for the high-side FET is referenced to ground but should be referenced to the source of the FET. If you look at Vgs of that FET you will see that it goes very negative. That should not happen. As Chris says, driving the totem-pole correctly is complicated.

 

[mading2018]

I have done like this so far, but do you think it is okay that the waveforms of Q1 and Q2 are not completely constant?
The clock singlas (CLK1 and CLK2) looks okay, but thats how I really want the Q1 and Q2 to be.

According to this source as you showed me Chris, there should be current spikes when AC is going through the zero crossing: https://www.ti.com/lit/an/slyt718/slyt718.pdf
so thats looks okay. But maybe the PFC is not the best, but it can't be closer than that maybe.

Your gate drive voltage for the high-side FET is referenced to ground but should be referenced to the source of the FET. If you look at Vgs of that FET you will see that it goes very negative.

Yeah, I know, but if I do that. Q1 and Q2 looks so strange? The value just increasing.

 

[alec_t]

Q1 and Q2 looks so strange?

Q2 gate drive look ok, but Q1 gate needs to track Q1 source. It may look strange, but that's the way it should be.

 

[mading2018]

Q2 gate drive look ok, but Q1 gate needs to track Q1 source. It may look strange, but that's the way it should be

Okay, I see. Then I assume it works quite okay. (you can the curve in the attached image).
Maybe its bad to compare with that image ("waveform.png") from the report, cause that image represents more the CLK1 and CLK2?

 

[ChrisP58]

Yes, I think have some more knowledge how do the switching for totem-pole now, If I could do something similar by implementing the dflipflop with ANDS grinds as you recommended me to do with the interleaved PFC, it may work for the Totem-pole PFC.

--edit--
could i use a BV voltage source to get an delay, and to obtain the same waveforms characteristics for Q1 and Q2? It looks like I need quite a long delay (a halfperiod) before Q2 can start to operating.

The power architectures of interleaved PFC and the totem-pole PFC are completely different. The concept of a d-flipflop to alternate the one gate signal between the two switches in the interleaved design is invalid in the totem-pole system.

Did you actually read the contents of the link I posed in #48? Or are you just trying to duplicate the waveform without understanding it's description?

 

[mading2018]

The power architectures of interleaved PFC and the totem-pole PFC are completely different. The concept of a d-flipflop to alternate the one gate signal between the two switches in the interleaved design is invalid in the totem-pole system.
Did you actually read the contents of the link I posed in #48? Or are you just trying to duplicate the waveform without understanding it's description?

It should alter I think, first Q1 is ON, where Ton should be much longer (long enough to be on during the positive side of the AC voltage waveform), and
than Q2 is ON (Q1 OFF), long enough to be on during the negative side of the AC voltage waveform.

Yes I have read it, but since it is complex for me to understand, I am trying to obtain Q1 and Q2 only and not Q3 and Q4. (I also have only Q1 and Q2 in my topology).

 

[ChrisP58]

It should alter I think, first Q1 is ON, where Ton should be much longer (long enough to be on during the positive side of the AC voltage waveform), and
than Q2 is ON (Q1 OFF), long enough to be on during the negative side of the AC voltage waveform.

Yes I have read it, but since it is complex for me to understand, I am trying to obtain Q1 and Q2 only and not Q3 and Q4. (I also have only Q1 and Q2 in my topology).

I don't understand how you can make it work without Q3 and Q4. As I read the 3rd and 4th paragraph under Introduction, they seem to be the primary parts of the topology.

 

[mading2018]

I don't understand how you can make it work without Q3 and Q4. As I read the 3rd and 4th paragraph under Introduction, they seem to be the primary parts of the topology.

I have started from scratch a bit. it looks like this at the moment. The circuit picture shows my topology, where only two switches exists.

 

[alec_t]

Remove the ground connection from V2. Then, perhaps, the current through the inductor won't be 3000A .

 

[mading2018]

Remove the ground connection from V2. Then, perhaps, the current through the inductor won't be 3000A .

Yes, it did help , thank you alec_t

Do you how could I implement GTDR from the IC-circuit to this...? I mean the waveforms looks good, but I guess I need to have GTDR somehow.