On PDF page 12, it certainly does mention a "start" and "stop" bit.
First you have to select serial mode with fixed voltages on pins 2,3 and 4.
The you enable serial mode with a pulse on FQ_UD
Clock in your 50 bits of data and another pulse on EQ_UD loads those 40 bits.
If you look closely at figure 10, it suggests a reset, but at that point I'm a little confused.
Hi KISS,
Are you by any chance talking about the WCLK and the FQUD signals?
I regard them both as "clocks", where one is the bit clock (WCLK) and one is the word clock (FQUD) where the word is 40 bits long (32 freq bits and 8 control bits).
Also, try this as a thought experiment: think about clocking in this 40 bit group i will write out one byte at a time:
0x00 0x00 0x18 0x00 0x00
notice how this is left and right symmetrical, and looking at that center byte we have in bits:
00011000
and this is also left and right symmetrical.
What this means is the order does not matter which way we sent the bits nor the bytes, it has to produce either one frequency or the other, and the two possible interpretations given reversed bytes only are:
0x00 0x00 0x18 0x00 [0x00]
[0x00] 0x00 0x18 0x00 0x00
where the control byte is in brackets.
These two frequencies can easily be calculated.
Now if the bits are reversed, then we would have a whole word as:
0x00 0x00 0x18 0x00 0x00
once again because that center byte is left to right and right to left symmetrical.
That means we have the same two possibilities if the bytes are also reversed:
0x00 0x00 0x18 0x00 [0x00]
[0x00] 0x00 0x18 0x00 0x00
Furthermore, if we send the word with the assumption that the first form above is the correct one and it is not, then we will get the 'other' frequency. Vice versa, if we send the second form and it's not right we would get the 'other' frequency. So if we send both 40 bit words (after purposely reversing the byte order for one), we should see both frequencies one way or the other, and we DO NOT see these frequencies.
Sending the bytes in parallel though works very well.
The code i use looks almost the same as the links i followed for various implementation, but i'll look this next link posted by mvs sarma and see what i can find.
I did notice though that in that link the three data lines that are supposed to be either pulled high or low are not connected, and they should be for clarity. That's how this gets into serial mode to begin with right (and a WCLK and FQUD clock too) ?