Advice on Process Simulator using Split Ranged PLC Outputs

I have an application where I want to test a PLC programme. In the past, working with DCS systems, I have used process simulators that had been built by the companies I worked for. The principle is that an analogue output which would normally go to say a control valve, is filtered to simulate a process, (i.e. time delay etc.)

This signal is then feedback to an input to complete the control loop. As far as I can tell these simulators are basically RC circuits. I have no problem with that. However, I have a situation where the PLC output is not the usual 4 – 20mA. We are what we call ‘split ranging’ an output, (actually using 2 outputs), to drive 2 control valves. One valve responds to 4 – 12mA, and the other 12 – 20mA. I wish to create a simulation of the process using these two outputs, but I need to sum them such that my return signal is 4 – 20mA. If I can subtract 12 mA from the first signal and then add the remaining 0 – 8mA to the 4 – 12mA signal, I shall have my 4 – 20mA. I came up with the attached drawing.

Would this work? I am assuming that the optimum setting of the variable pot would be 2KΩ? Is it felt that the attached circuit would subtract 12mA in a stable manner? If not, can anyone suggest something that will? Thanks, Chris.

hi,
Looking at your circuit it shows the high and low current loops having a common 0V return, is this correct.?
Or is the 4-12mA and 12-20mA split off from a single 4mA to 20mA current loop.?

I could simulate the circuit using LTspice, if you give me some more details of the 4-20mA source.

hi,
This sim shows the operation IF the two current sources are isolated at their sources.

There is some non linearity in the composite current into a 250R assumed load.

Common Ground

Hi Eric,

Thank you very much for your reply. Yes, the two 0V do have a common return. as for the filtering, I am thinking that this may not be exactly what I want? The process this is to simulate could have a lag of up to 1 hr? If I use a resistor ahead of the capacitor then this will affect the output current. Perhaps I should instead be looking at LC circuits? If I use an inductor to feed the capacitor, that should cause an initial delay after which the capacitor will charge up. Presumably that will give me a typical capacitor charge curve in my output current? By switching various capacitors in parallel to the first, that would give me slower charge times. To simulate further orders of lag I could repeat the LC circuit in parallel with the previous capacitor, and so on? (see attached). What are your thoughts on this? Thanks,

Chris.

hi Chris,
If you download the free LTspice simulator, I could post the sim asc file.

Hi Eric,

Yes, I do have the LTspice simulator. Thanks,

Chris.

Britman said:

Hi Eric,

Yes, I do have the LTspice simulator. Thanks,

Chris.

Click to expand...

hi,
Here it is.

Britman said:

............. I am thinking that this may not be exactly what I want? The process this is to simulate could have a lag of up to 1 hr? If I use a resistor ahead of the capacitor then this will affect the output current. Perhaps I should instead be looking at LC circuits? If I use an inductor to feed the capacitor, that should cause an initial delay after which the capacitor will charge up. Presumably that will give me a typical capacitor charge curve in my output current?

Click to expand...

If you need to simulate an hour lag, that's very difficult to reliably do in analog and would take some very large value components. Do you actually need an RC looking exponential output or would a step function (digital) delay be sufficient?

Either way I believe some sort of digital approach to the delay is needed.

Britman said:

Hi Eric,

Yes, I do have the LTspice simulator. Thanks,

Chris.

Click to expand...

hi Chris,
I would be interested to help with this project, lets see your LTS files when ready.

P.S.

Just for further info; the PLC that this simulator circuit is to be connected to is a Wago, employing a 750-841 processor.

Hi Carl,

Yes, I have been thinking about that. I haven't yet worked out exactly what size capacitors I would have to use, but I guess they would be pretty big? Unfortunately this control system is analogue, so a step change delay would just give that: a delayed step. The real process itself will have capacitance as well as lag, as the increase in temperature via the heating medium has to be transferred from the vessel jacket to the vessel itself. This reactor is about 8 ft in diameter and about 17 ft tall so there is a lot of steel to heat up before the internal product sees a temperature change. I am not too familiar with modern op-amp circuits, but perhaps there is one that behaves as a large capacitance? Does anyone know if there is one out there? Thanks, Chris.

Eric,

I thought I had just sent you a reply, but I don't see it up here. Did you get the one giving the details of the actual vessel size in the real process, and a question about an op-amp based circuit to simulate a large capacitance? Thanks,

Chris.

For a op amp LP filter with a RC time-constant of 1 hour (3600s) and a 1 meg resistor would require a capacitance of 3600uF. Such a capacitance can be readily found, but they are electrolytic types and can have significant leakage that could affect the time constant. You'd have to check the leakage of the actual capacitor you would use to determine how serious a problem that would be.

Edit: You could also use a 10 meg resistor with a CMOS op amp (for high input impedance) with a 360uf film type capacitor (although they are rather expensive). Film capacitors have much lower leakage than electrolytics.

Thanks Carl,

The CMOS op-amp definitely sounds like more the way to go? I just tried playing around with the RC circuit schematic using LTspice, but I couldn't get more than a few milliseconds delay, no matter what values I tried. I was hoping for a decent lag and then a good ramp up to the final current. Do you know of any op-amp circuits out there that are ready designed to achieve this kind of thing? Thanks,

Chris.

Below is an op amp connected as an RC all-pass type filter, which acts as a delay line for a step input. For the values shown it gives a delay of about 3600s before the output exponential rise starts. It uses one of the CMOS op amps available in LTspice but most CMOS rail-to-rail type op amps should work.


View attachment RC Delay.asc

Thank you, thank you, thank you!!!!

Hi Carl,

Thank you so much for the help. The delay and waveform are just what I'm after. I take it that V1 and V2 are actually where I would make the input and output connections? I haven't had a chance to study it yet, but that was my first guess.

Chris.

Ah, just looked again. I see there is actually an output there.