Bipolar high voltage +/-100V@2A for ultrasound pulser

[Patt]

Hello,
I’m designing an ultrasound pulser-receiver using either the HV7360 or HV7361. Both components can handle ±100V and outputs can source and sink up to 2A current. However, I’m struggling to find a suitable power supply that can deliver ±100V at 2A.

I´m not a experienced hardware designer, so I searching for commercial AC/DC or DC/DC ±100V converters, but none seem to meet the 2A requirement. I also reviewed the HV7321, HV7351, or STHV748 demo boards, but non of them provide an explanation how to generate the required bipolar high voltage.

Could you suggest a suitable solution? Any help will be appreciated.

 

[rjenkinsgb]

What is the pulse duration and duty cycle?

If the transmitter is only powered eg. 1% of the time, the average power draw would be around 20mA (though a bit more needed in practice, especially to give an acceptably short start-up time).

With large reservoir capacitors to maintain adequate voltage for the duration of the pulse, a rather smaller PSU should be adequate.

 

[Patt]

Thank you rjenkinsgb for you reply.

The ultrasound transducer need to be applied a rectangular +/-100V burst at 1MHz. The burst will be configurable from 1 to 16 cycle-pulses, and it will be applied once every 30 minutes.

Based on what you mentioned, would the ECL30UD03 (an AC-DC converter) along with the F02CT (a DC-DC converter with a 12V input and ±100V @ 50mA output), be sufficient to power a US transducer with an impedance of 84.48Ω (magnitude) and -75° (phase) at its fundamental frequency? I´m worried by the 50mA output current of the DC-DC converter.

 

[AnalogKid]

The problem with something like the F02CT is that while its output power appears to be ok for this, it is designed for a continuous low-current load rather than a very short, very high current. One solution is relatively large capacitors on the outputs.

16 cycles at 1 MHz is a 16 microsecond current burst. Using a linear approximation for capacitor discharge, that works out to a 3.4 V sag in capacitor voltage with a 4.7 uF cap. IOW, if the DC/DC converter charges a pair of 10 uF output capacitors up to +/-100 V, then the capacitor voltage will sag down to something above 95 V during a burst. In the datasheet there is no maximum output capacitance spec, which is good.

How constant does the peak voltage have to be during a burst? The solution might be your DC/DC converter followed by a linear regulator. The datasheet says the output is proportional to the input, so running it on 13 V instead of 12 V should increase the output voltage enough to cover the regulator headroom. The regulator doesn't have to be great, but it has to be fast.

Or something like that.

ak

 

[rjenkinsgb]

16 Cycles at 1MHz means 16 x 0.5uS current pulses from each rail.

So 2A for 8uS each rail total, worst case.

The basic rule for capacitor discharge (or charging) is 1 Farad will change by 1V per second per 1A current.

So scaling capacitance and time, a 1uF cap will charge/discharge by 1V per microsecond per amp.
A 22uF cap on each rail should droop less than 1V during the pulse sequence.

I'd probably go with 47uF or 100uF as a convenient value - just make sure the ripple current rating is high enough, and preferably use 250V caps. (Capacitor lifetimes are very short if run near any of their max ratings).

2A for 8uS discharge would hypothetically need 50mA for 40 times as long, 320uS, to recharge.

Due to the very small voltage drop on the caps, the load change on the inverter will likely be so slight it it probably wont give much current at all, but will bring the caps back to full voltage within a few seconds to a minute or two.

The only time it would experience a high load is when the device is switched on when the caps are discharged.
You could use series resistors to limit the initial current, if the inverter could be overloaded by it.


You could also add in a voltage sense circuit that shuts off the inverter once the caps are fully charged & cuts it back in again when the voltage has dropped a few percent? That would minimise power use and extend the inverter life.

 

[Tony Stewart]

±100V at 2A with 2% load regulation means ESR = 2V/2A = 1 Ohm
16 us duration means C= Ic*dt/dV = 2A*16us/2V = 16 uF ESR*C > 10us, ok.
This is easily doable with a low ESR Alum e-cap.
Charging up CV^2 = 16e-6*1e4 = 160 mWs with 50% eff.

 

[Patt]

sorry

 

[Patt]

Thank you all for your contribution. You all help me a lot.

In case a serial resistor to prevent a sharp initial current, I suppose a 50ohm would be a proper one (100V/2A). However it should be a P=I^2xR=2^2x50=200W resistor. It is not very common. May be four resistor of 12.5R@50W in serial or four 200R@50W in parallel might be an option.

In the other hand, rjenkinsgb, what do you mean when you say "if the inverter could be overloaded by it"?
Thank you again.

 

[rjenkinsgb]

rjenkinsgb, what do you mean when you say "if the inverter could be overloaded by it"?
Thank you again.

Some inverters cannot stand being run in to a high value capacitor, as the initial output current may overload them.

Others can stand a temporary high load current without problems.

If there is a chance of overload, series resistors between the inverter outputs and reservoir caps (not at the load side) would limit the current and protect the inverter.

At it's low current, they could be quite high value - possibly 470 Ohm or 1K even.