bootsrap (bjt) help for free running ramp gen

[wakoko79]

Hi again sirs! Here is my situation:
We have a design problem in the school in which we are tasked to create a free running sawtooth generator with a [bootstap ramp generator] + [schmitt trigger].
I was given the task of creating a 1-5V ramp that has a frequency from 100 to 3kHz.

We were given choices on how to do this:
1) BJT ramp gen + BJT schimtt
2) OPAMP ramp gen + BJT schmitt
3) BJT ramp gen + OPAMP schmitt
** both OPAMP not permitted.

I took BJT ramp gen + OPAMP schmitt since opamp schmitt is a lot easier to do than its bjt counterpart.

The schmitt(non-inverting) was very easy to do, and its current draw is negligible (~10-20uA) compared to the emitter current (minimum of 4mA).

I'm fairly familiar with the operation of the BJT ramp gen.


*LTP= 1V
*UTP= 5V

Now, my problem is that the output ( point B ) doesn't go up as soon as it hits the LTP of the schmitt.

Initially, I thought it was because of the bootstrap capacitor. Here's my line of thought:
Ideally, the voltage across this bootstrap capacitor (C2) would be Vc2=15-Vd - (LTP). As the voltage across C1 increases the output follows (point B) then point C also needs to go up. the moment point C rises, the diode will cut-off, so it means the bootstrap cap will provide current, right? As this happens, the voltage across C2 slightly falls. When point B hits UTP, the schmitt will change state making transistor Q2 to turn on. Points A, B and C rapidly falls, but as soon as point C hits the voltage needed to turn on the diode, point C will be stuck at that voltage which means point B will also be stuck at its current voltage while point A happily goes down which in turn causes transistor Q1 to cut-off. Since the bootstrap capacitor lost some voltage across it while charging C1, point B will not reach LTP as fast as we want it, it needs to recharge for some time. I THOUGHT that was the reason why there was a lag time before point B starts to climb up again.

But as I see the waveforms now, I found that I was some how, wrong. The output of the schmitt (point D) should have changed state AFTER the lag time of point B and not BEFORE. More intriguingly for me, the schmitt changes state as soon as point A reaches some low voltage (i think Vcesat,q2).

Can anyone please tell me what's happening here and help me out? T_T

I tried to put a buffer opamp between point B and the schmitt input, I also tried removing the schmitt altogether and instead put a sig gen. I found out that indeed, it's not the schmitt.

I thought putting a resistor between point C and the diode would help so that point C won't be stuck when the diode turns on. It worked really well both in simulation and actual testing, gave me a very good sawtooth signal. Initially, I thought putting a low resistance(10 ohms) would be just fine but it didn't work, point C was still stuck. I then put 1k and the thing came out right. The thing is, point C won't go over 15V, thus making the diode useless. Also, there will be a current running through the resistor I just put (between diode and point C) since it has a current drop and I think this will affect the linearity of the output.


PS: the deadline of this DP was extended for 1 week (since we only meet once a week) since none of my classmates did it. Only the bootstrap from 0 to some voltage was taught to us, and i thought doing it for 1V to some voltage will be as easy. Me wrong, me stupid.. haha..

 

[carbonzit]

Sorry, can't help you. I just wanted to comment what a pleasure it was to read a post by a student that, for a change, was written by someone obviously well engaged with the subject of their studies, and not consisting of a plea to "do my homework for me so I can get a passing grade (who cares if I actually learn anything?)".

 

[wakoko79]

Sorry, can't help you. I just wanted to comment what a pleasure it was to read a post by a student that, for a change, was written by someone obviously well engaged with the subject of their studies, and not consisting of a plea to "do my homework for me so I can get a passing grade (who cares if I actually learn anything?)".

too bad.. >.<

I think my conscience won't let me take my diploma if I make people do my homeworks for me without thought. Passing a course without really understanding it is much much worse than failing it, I think. haha..

 

[crutschow]

It took me awhile after simulating the circuit to understand what was happening. You were correct about it being related to the bootstrap capacitor. The time during the flat part of the waveform is when C2 is being recharged through D1 due to the charge lost on C2 during the bootstrap ramp part of the sweep. The flat voltage at "B" is where D1 starts to conduct and recharge C2, and this current, due to the voltage drop across R6, keeps the voltage at "B" at about 1V. The voltage at "B" thus doesn't start to rise until Q1's base voltage (voltage across C1) is greater than about 1.7V. Since C1's voltage starts at essentially 0V, the time it takes to go from 0V to 1.7V is the delay you see.

To reduce this time you can reduce the charge lost during the ramp. Increasing R1 to 18k and reducing C1 to 0.1uf (to maintain the same ramp time-constant) will do that and significantly reduce the flat time. Also try simulating for a longer time to allow the circuit to fully settle into its normal operation (at least several hundred milliseconds).

Reducing the value of R6 also helps.

 

[wakoko79]

Thanks =).

I'll try to do that. Though, lowering R6 would mean higher current through it while charging C1, which means higher base current for Q1 which in turn will reduce the linearity even more. Increasing R1 then would further reduce linearity since it means lower current for charging C1. I guess you really can't have free lunches. Ugh, things like this is why I love opamps so much. I'll try to figure things out though. =)

 

[crutschow]

You could use a darlington or a Sziklai pair for Q1 to lower the base current and improve linearity.

 

[Roff]

You can make R6 a higher value if you add a PNP emitter follower to drive the bootstrap capacitor. The PNP will sink the recharge current. Keep the NPN emitter follower as is.

 

[rlaurellano]

Hi!

We have the same exact project but I need help in modifying the bootstrap ramp generator. Your output goes from 0 to 5 volts. How can you make it go to say like, -5 to 5 volts? The internet and our book has failed me T_T Thanks!

 

[ericgibbs]

We have the same exact project but I need help in modifying the bootstrap ramp generator. Your output goes from 0 to 5 volts. How can you make it go to say like, -5 to 5 volts? The internet and our book has failed me T_T Thanks!

Deleted.

 

[crutschow]

We have the same exact project but I need help in modifying the bootstrap ramp generator. Your output goes from 0 to 5 volts. How can you make it go to say like, -5 to 5 volts? The internet and our book has failed me T_T Thanks!

You could run the Q2 emitter and C1 to -5V instead of ground. C1 will then charge between -5V and the upper setting on the comparator.

 

[rlaurellano]

You could run the Q2 emitter and C1 to -5V instead of ground. C1 will then charge between -5V and the upper setting on the comparator.

It worked like a charm! Thank you very much sir!

But a friend of mine mentioned something about possibly using both npn and pnp transistors on the bootstrap circuit so that the output can swing to the negative rail. I have racked many a brain cell trying to figure how to configure that and I wonder if there is even a probable solution for that. Would you happen to know anything about this? Thanks again!

 

[crutschow]

You could use an NPN and a PNP as a push-pull driver but you would need to add a couple diodes between the two bases to properly bias them, similar to that done in audio amps, to minimize crossover distortion.