Guys I have a question..
Lets say I am receiving digital serial data. For example 1Gbps. I need a clock to sample such data and be able to retrieve it, since it could be totally random.
I need to extract such clock from my data, in whats called clock recovery.
Now my questions are:
1. Do I HAVE to use PLL to recover my clock? (phase locked loop)
2. If yes, is there anyway I can do it with all digital PLL?
3. Anyway I can simulate such work in verilog?
4. If I am receiving 1Gbps, could it become 900Mbps due to noise, for example?
Thanx.
Lets say I am receiving digital serial data. For example 1Gbps. I need a clock to sample such data and be able to retrieve it, since it could be totally random.
I need to extract such clock from my data, in whats called clock recovery.
Now my questions are:
1. Do I HAVE to use PLL to recover my clock? (phase locked loop)
2. If yes, is there anyway I can do it with all digital PLL?
3. Anyway I can simulate such work in verilog?
4. If I am receiving 1Gbps, could it become 900Mbps due to noise, for example?
Thanx.