Cmos dc characteristics

Is regions in cmos dc characteristics based on experimental results? If not help me by explaining how nmos and pmos goes into saturation or linear or cutoff in each regions

In a CMOS inverter (the simplest CMOS circuit) when the input is a logic low (0V) the P-channel MOSFET is full on and the N-channel MOSFET is cutoff, thus the output is a logic one (V+ supply). When the input is high (V+) the N-MOSFET is full on and the P-MOSFET is cut off, thus the output is logic 0 (0V).

Manuv16589 said:

Is regions in cmos dc characteristics based on experimental results? If not help me by explaining how nmos and pmos goes into saturation or linear or cutoff in each regions

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hi,
Not directly related to your question, but you may find this pdf will help with some of the details.