Still here ... I have the Z80 pensioner
under PIC control, signals more or less as DS ... the Reset ( PIC generated) shows how first instruction fetch is achieved ,(M1 & Read ) the wait (PIC generated ) allows control over memory access. just in the process of designing a better control circuit... ( Bus Pirate is ace )
Z80 clock at +- 20khz
HE if your reset switch bounced during or after zero state , or not low for the 3 clocks , then Z80 = unknown state ?
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