Couldn't turn on and off the logic MOSFET....

[Styx]

But With Common-Collector there is chance of shoot-throughs (common-emitter doesnt have this)

I'm not saying common-emitterCommon-collector is the better circuit, equally I am not saying Common-collector is the better one (although this is the arrangement I would go for). Both topologuies have their advantages and disadvantages and their uses.

Best thnig about engineering: No real wrong answers, just better answers

 

[Nigel Goodwin]

But With Common-Collector there is chance of shoot-throughs (common-emitter doesnt have this)

In what way?.

 

[Styx]

you get them during a HIGH to LOW input to the leg - TheOne has already shown that with FET-based bridge leg. he same stands up true for BJT phase leg.

There is a finite time it takes to switch a device ON and OFF. It is worse for switching OFF the P-type/PNP since it takes alot longer than the N-type/NPN to turn-on.

Thus there is a finite time when both devices are ON (be it in their active region) Thus they dissipate alot of power and over-stress the devices.


There are two causes of shoot-thoughs. Bad driving and thus turning on both switches in a leg OR during a transition during the switching period.

It is due to teh switching times that I always put interlock into my commutation stage, thus ensuring that when I turn OFF the device that is on (in a leg) there is a period before I start to turn ON the other device, thus giving the other device to turn-off fully. This time is based of the switching charateristic of the switches being used



It is this type of shoot-through that I was stressinb when Fabbie said his FET's were getting hot.

I think he interpreted that shoot-through suggestion as a control "both switches ON" type. When I ment a switching shoot-through


The switching shoot-through will be inherent in hsi design. Without incorportating a dedicated drive per switch and added interlock logic, the topology I chose slows down the gate voltage to the FET's and thus slowing down the time it take a gate signal to reach the threshold voltage level.

Essentally a crude method of making interlocks.

 

[Nigel Goodwin]

you get them during a HIGH to LOW input to the leg - TheOne has already shown that with FET-based bridge leg. he same stands up true for BJT phase leg.

There is a finite time it takes to switch a device ON and OFF. It is worse for switching OFF the P-type/PNP since it takes alot longer than the N-type/NPN to turn-on.

I see what you mean, but I wasn't suggesting simply changing the transistors over, but using a correctly designed circuit for the configuration I suggested. I would tend to cross-couple the bottom transistor of one leg with the top of the other - this avoids any potential problems like that. It obviously introduces the possibility of turning all four devices ON at the same time (which isn't a good thing!) - but you can counteract that either in hardware, or by carefully written (and hopefully bug-free) software.

In any event, S/C failure of any one device in an H-bridge is likely to be fairly catastrophic in a similar fashion :lol:

 

[Styx]

Yer I know - H-briges are are not he most fault-tolerant things around. makes FMEA's easier
"what happens if this occurs - Blows up"
"what happens if this occurs - Blows up"
"what happens if this occurs - Blows up"
...

Yes tying Gates to the other side will eliminate the posiibility of a shoot-through since it's turn-on/off is now descretly tied to the the other device turning-off/on

I just wanted to stess that there are other factors IF someone wanted to up the power handling on a H-bridge and was not giving switching times of power devices the respect they need

 

[TheOne]

Here is nice link showing all the waveforms and some basic theory

http://www.mcmanis.com/chuck/robotics/tutorial/h-bridge/bjt-selection.html

 

[fabbie]

Makes no difference even with a 20K. You most probably need a big cap at the top as well.

I found this strange, so after trying another FET model I re-run the simulations. This time the delay was enough with a much smaller value of C (100pF) and the 7k resistor suggested by Styx originally.

That specific model must have been flawed as it made no real difference if I had a 1k gate resistor or 100k!

Hey, do you mind teaching me how to calculate the capacitor and resistance value?
Here written in my MOSFEt datasheet for the N-Channel MOSFETs there are input capacitance and output capacitance each with the typical value of 480pF and 280pF. I suppose the input capacitance is for charging and output for discharging.
Anyway, how did you manage to get the value of 7K resistor and 100pF capacitor? isit through trial and error?

 

[Styx]

Basically P-types have a higher gate capacitance that N-types.

If you know the difference between them, that capacitance value should be added to the N-type (ie in parallel with the Gate-Source terminals) To make it look more like a P-type (as far as capacitance)

The resistance value is split into two

Turn-off needs to be as low as possible 10R is good

For turn-on, which you are trying to slow down to stol switching shoot-through it needs to be high enough so that it slow the rising gate voltage such that the Vthreshold is only reached ONCE the other device has turned off.


Originally I questioned the gate capacitance that "TheOne" was using since his results didnt sound right. He did end up swaping changing the device

 

[TheOne]

Here is drive circuit using both N devices per leg where the supply for the upper device is established by a bootstrap arrangement. It is a bit more complicated.

Simulation results indicate a working circuit, however one should carefully monitor the two gate signals in practice for any overlap (with some current limit like a 12v bulb placed in series with the drain of Q1) and make adjustments (gate resistance/capacitance) to the calculated values, for the type of device used.

 

[Oznog]

I do not see what purpose D5-R10-R5 and D3-R4-R3 serve. Why are they here?

You have used an NMOS for the pullup driver. This is a problem since the gate voltage needs to be higher than the output, but there is no voltage above the 12v rail to drive it so the output is very limited and prone to distortion. A PMOS is the proper choice. The gate signal will need to be inverted.

 

[TheOne]

I do not see what purpose D5-R10-R5 and D3-R4-R3 serve. Why are they here?

Faster off than on-time's

You have used an NMOS for the pullup driver. This is a problem since the gate voltage needs to be higher than the output, but there is no voltage above the 12v rail to drive it

Yes there is ~12V (12-0.7V)

so the output is very limited and prone to distortion. A PMOS is the proper choice. The gate signal will need to be inverted.

No, N types are better than P

 

[Oznog]

No, N types are better than P

But you can't use an N here! The highest voltage that can hit that gate is 11V. The threshold for an IRF510 is 2-4v, so for the weakest of output current you will only be able to drive 7v to the output. For more realistic output currents, you're talking 4v to 5v output. This will probably overheat the MOSFET outright.

In general, N channels have lower on-state resistance and lower gate capacitance. But they make plenty of P-channel devices with better stats than an IRF510.

Lowering the switching times is often disasterous, but it depends on your switching freq. Each slow transition, on or off, creates a crapload of heat which can be many times greater than that generated by rds-on heating.

Just what are you trying to do? Is this a motor controller, audio amp, or what? Is it supposed to be half of an H-bridge? Is it driven by a PIC? How much current is it supposed to drive?

I do not yet understand why there is a pulldown transistor. Is this supposed to drive a transformer or something? A PWM used to drive a motor, etc would not need to pull the output low when the high side transistor is off.

 

[Nigel Goodwin]

But you can't use an N here! The highest voltage that can hit that gate is 11V. The threshold for an IRF510 is 2-4v, so for the weakest of output current you will only be able to drive 7v to the output. For more realistic output currents, you're talking 4v to 5v output. This will probably overheat the MOSFET outright.

That's the whole point of him posting the circuit, C1 is a bootstrap capacitor and provides a higher drive voltage for the top transistor, it's an extremely common technique!.

 

[Styx]

Boot-strapping is fine, Does mean a slightly more complex driving arrangement

ie for a leg you now have to send the complement to the N-types.

with a P-type and a N-Type in a leg you just had to send the signal

When you start getting to higher voltages (where using a P-type is way out of the question). Floating gate drives for the upper channels are needed := opto's for the signal and some form of isolated DCC converters for the power.


Then the fun starts