It's a synchronous counter, but there's an asynchronous reset line involved, and gating the output of a binary counter is pretty much the perfect example of a glitch generator. If the two wires going to the NAND decoder gate have different lengths, the NAND gate inputs have different capacitive loadings/threshold voltages, or the two counter flip flops have slightly different clock thresholds, or there's enough induced noise in one of the two lines, you have a race condition and an early load.
The chances of it will probably be pretty low considering the edge speeds involved, but it isn't a good idea in any case.
Actually, a ripple counter would probably be (marginally) preferable since it would always transition the lower bit first. The NAND gate would then see
"01" -> "00" -> "10" when going from '7' to '8'.