Counting sequence

[MrAl]

Hi again,

That looks pretty close although i did not check the schematic itself your wording sounds right, except for the very last line for Y7. For the state of where Y7 goes low, you have three output bits that have to go high yet you only show two connections. So you need to add one more connection to one of the NAND gates to get that last bit to go to a high during Y7.

I guess you could check the schematic in a simulation.

Also note that if we went through the Boolean logic and minimized that we may come up with a simpler solution. Im not sure if you are into doing stuff like that or not though. This would involve working with statements like:
bit 0=(AB'+A'B)*C'

or something like that (that's just a random example), one for each output bit, then trying to find the simplest solution. There is always a chance that this would lead to a simpler solution, sometimes much simpler too, but sometimes none simpler.

 

[digitalp]

Hi again,

That looks pretty close although i did not check the schematic itself your wording sounds right, except for the very last line for Y7. For the state of where Y7 goes low, you have three output bits that have to go high yet you only show two connections. So you need to add one more connection to one of the NAND gates to get that last bit to go to a high during Y7.

I guess you could check the schematic in a simulation.

Also note that if we went through the Boolean logic and minimized that we may come up with a simpler solution. Im not sure if you are into doing stuff like that or not though. This would involve working with statements like:
bit 0=(AB'+A'B)*C'

or something like that (that's just a random example), one for each output bit, then trying to find the simplest solution. There is always a chance that this would lead to a simpler solution, sometimes much simpler too, but sometimes none simpler.

Okay.

 

[digitalp]

Hi,

Well you are going to have to explain what that schematic is because that bares no resemblance to the schematic i suggested. What i suggested was a neat and orderly process to obtain the correct output codes. What that schematic looks like is a mess of connections and i dont even see where the outputs are. So maybe you could explain a little about what you were trying to do there.

The schematic i was talking about is partially drawn in the attachment which shows only the basic parts not all the interconnections.

I have attached the diagram with correction to y7.
But my simulation was unsuccessful.
Where could be my mistake?

 

[MrAl]

Hi,

Ok now that we have moved to the schematic, there are a number of mistakes in the connections. As soon as they are fixed this should work just fine, so you are getting very close now

First, the connections to U2 look like the VCC connections might be shorting all the input pins to VCC. Move U2 over to the right a little and draw all the connections again, making sure to leave room between the pin ends and the VCC lines so they dont touch. unless of course they really have to go to VCC, but maybe a 5 input gate would be better (read on).

Next, for BIT 3, all the inputs go to VCC so how could that possibly work that way. You have to go over that and correct them.

Also, the output Y0 of the 74LS138 goes to VCC ??
An output never gets tied to VCC, but it may be left open. Only the inputs get tied to VCC when not used, or possibly ground depending on the logic function, but never the outputs.

So go over those connections and correct them, then maybe double check all the connections and note that for BIT 2 there is only one 'high' ever needed and that is for only one state, so the NAND gate for that bit only needs one input or else use an inverter. Also note that one of the other bits requires a 3 input NAND gate, so maybe you can find a dual 5 input NAND gate to use one section for BIT 0 and the other for the other BIT.

 

[digitalp]

For 0001: Y1 connected to pin A 0f bit 0.
For 0001: Y2 connected to pin B 0f bit 0.
For 0010: Y3 connected to pin A 0f bit 1.
......

 

[MrAl]

Hello,

Did you post here again by mistake, because that last post does not make any sense.
Check your PM conversations.