Hi, can anyone make a vhdl (using quartus software) from this mealy diagram?? i got the code already but there's no out put in my functional stimulation. The output is remain zero. Suppose, the output got 1 and 0 also. Thanks for helping
your logic is fine, i dont know abt the syntax of vhdl, i worked in verilog
you should check for syntax error, and sumtime running a program in new project help too
you didnt define the clk signal
for simulation you require a clk signal
start a loop for clk
your logic is fine, i dont know abt the syntax of vhdl, i worked in verilog
you should check for syntax error, and sumtime running a program in new project help too
you didnt define the clk signal
for simulation you require a clk signal
start a loop for clk