RCinFLA
Well-Known Member
The reason is R2 is higher value then mirror resistor allowing Q2 drain to drop lower then its gate voltage. The variance will get greater as Q2 get closer to saturation.
Different FET's will be more or less sensitive to the reaction to lower Vds voltage on the current mirror.
Different FET's will be more or less sensitive to the reaction to lower Vds voltage on the current mirror.
