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Hi Eric,hi,
regopmode address 0x01
data bits
0 = FSK/OOK : change allowed in SLEEP Mode ONLY
01 = OOK
0 =Res
1 = LF mode
101 = rec mode rx
0,01,0,1,101 == 0x2D
Is the unit in Sleep Mode.?
E
Hi Eric,hi,
Used in your other thread:
"The SPI interface gives access to the configuration register via a synchronous full_duplex protocol corresponding to CPOL=1 and CPHA=0 in Motorola/Freescale nomenclature. Only the slave side is implemented."
E
My plot shows...using your program
Hi Eric,hi,
On the SDI line do you have a 10k pull up to +5v.?
I don't understand
Regarding the broken received signal, this could be because it's a tone???
E
Hi Eric,hi,
On the SDI line do you have a 10k pull up to +5v.?
I don't understand
Regarding the broken received signal, this could be because it's a tone???
E
Hi Eric,hi C,
How are you down level shifting between the PIC at 5v and the SX at 3.3v.?
C select, Clock and SDO [ MOSI]
E
Hi Eric,hi C,
Ref your PM.
If I follow the SX datasheet spec for the SPI, it suggests that the clock should be High at rest, going low for the Clock period. [you show it the opposite sense]
You say that you can Write/Read the SX registers OK with the Clock as shown in your image, if that is the case, I would move onto the next stage of the project.
E
Hi Eric,hi C,
You did post in an earlier post:
"The SPI interface gives access to the configuration register via a synchronous full_duplex protocol corresponding to CPOL=1 and CPHA=0 in Motorola/Freescale nomenclature. Only the slave side is implemented."
Which suggests a Clock High at rest, going low when clocked.
Your clip in #95 states CPOL=0.
One of the statements is incorrect.
As the SPI works OK using CPOL=0 I would say the 1st statement is wrong.
E
View attachment 104333