ci139
Active Member
there's an article explaining the I/O speeds on a different mcu basis -- but we can predict the input rate being apx 1 x sys clk from Figues 10-3 & 10-4 -- that incase there is some ideal sync. between sys-clk and incoming digital signal otherwise it's variable 1 to 2 sys-clk.-s e.g. at 20MHz you can read in at predicted average 14Msps or at least 10Msps - - - - that if you use external comparator to compare V.out V.set or incase of external ADC // assuming 4-bit parallel input (is supported by port masked input instruction ????????) // the 12 bit DAC can be fetched at 3MHz - versus - 1 bit comparator at 10MHz . . . . . . . . . rserving some time to do internal lookup we assume 300k / 1MHz MOS-Fet control rate - - - 3 or 1 µs "sys don't care" free wheeling - - - whatever the timing - the current limit for inductor+mosfet should be another external device sending it's "triggered" status to mcu
shortly -- without looking the code yet - but only the schematic - we can speculate the system being robust and not very flexy . . . unless the pwm modules have their own controllers and setting the pwm index does some miracles here ??? -- at max. clk/2⁸ (78.1 kHz) or clk/2⁹ (39.1 kHz) PWM cycle ??? -- related https://microchipdeveloper.com/8bit:10bitpwm
shortly -- without looking the code yet - but only the schematic - we can speculate the system being robust and not very flexy . . . unless the pwm modules have their own controllers and setting the pwm index does some miracles here ??? -- at max. clk/2⁸ (78.1 kHz) or clk/2⁹ (39.1 kHz) PWM cycle ??? -- related https://microchipdeveloper.com/8bit:10bitpwm