Digital chip input handling

[carbonzit]

Couple questions regarding handling the inputs to digital ICs (the chips I'm using are all in the CD4xxx series).

1. I have a project where I'm using a 4013 as a latch, and I want it to come up in the unset state when I power it on. I'm using this arrangement, which seems to work OK:

Question is, what values of R and C would be best here? (I don't mean super-optimized, just what will accomplish what I want, which is a reliable reset.) The trade-off here seems to be between A) a small C giving a shorter pulse vs a larger C, and B) a small R giving a faster pulse but loading the input more.

Basically, are these values in the ballpark?

Yes, yes, I know there are probably better ways to do this, like a one-shot, a 555 or something, but I'd rather keep this as simple as possible and not have to add another chip. It's not a precision application.

2. In the same project I'm setting the flip-flop by using a pushbutton switch connected to the set input. Since there's nothing else connected (no other gate), do I need to add a resistor to ground so that this input doesn't float when the switch is open? Would the same (4.7K) value be good here?

(Anticipating replies: no, debouncing isn't needed here. Multiple pulses don't matter.)

 

[AnalogKid]

Not to quibble much, but an edge with a 1 ps risetime still is an exponential or linear, or <whatever> ramp, an analog signal.

Speaking of the way hobbiests see the world, do you really think there is any ambiguity in the intent of danadak using the word "analog"? He was speaking at your level.

ak

 

[crutschow]

This TI & Toshiba apnote discusses it applies to all inputs, attached, as posted prior.

Meta-stability is not a concern for logic inputs such as SET and RESET.
Even if the input is initially bouncing or noisy or slow, it will go to a stable SET or RESET state, once the signal has settled.
How could it not?

 

[danadak]

Meta-stability is not a concern for logic inputs such as SET and RESET.

In asynch parts true, but synch reset/set types where clk and data (set/reset) have
setup/hold time violations.....?

 

[throbscottle]

If you can live with the active low inputs, the 74HC74 does the same thing and is specified as able to work with slow rising signals. I have one quite happy working away with a 4.7uF/47K combo tied to it's clock input (gives around a 1s delay).
OTOH it's a POR you have so you are using a pretty standard arrangement (well ok standard a couple of decades ago anyway!) so if it works, stick with it. I'd use a bigger resistor though, as crutschow says, and smaller cap.

 

[danadak]

The datasheet I am looking at :

https://media.digikey.com/PDF/Data%20Sheets/ON%20Semiconductor%20PDFs/74HC74.pdf

https://ch00ftech.com/wp-content/uploads/2012/05/74hc.pdf

Regards, Dana.

 

[AnalogKid]

In asynch parts true, but synch reset/set types where clk and data (set/reset) have
setup/hold time violations.....?

That is not the question in post #1.

ak

 

[eTech]

I have one quite happy working away with a 4.7uF/47K combo tied to it's clock input (gives around a 1s delay).

Hmmm....seems like those values should produce a delay of about 300ms...(?)

 

[carbonzit]

In asynch parts true, but synch reset/set types where clk and data (set/reset) have
setup/hold time violations.....?

My project doesn't use the clock or data inputs on the flip-flop; I'm using it strictly as a S-R latch. Maybe I should have stated that earlier.