Digital Counters Counts Sample External Frequency Wrongly

Please see the attached schematic. I am experimenting with a circuit for sampling an external frequency. The counters do not always count correctly. At first I suspected the breadboard and I replaced it with no success.

I would like to know if anybody understands what mistake I have in my circuit which results in wrong count. It seems to me the only reason could be timing. I also experimented with timbases of 8, 16, 64, 128, 256 and 512 HZ. But it looks like that a timebase with lower frequency produces less sever errors for counting the pulses.

The update pulse (UPD) and reset pulse (RST) are derived from AND gates and inverters fed by the outputs Qk, Qj and Qi of a 4040 counter which divides a 32768 HZ frequency obtained from a crystal controlled timebase. All ICs are bypassed by a capacitor from their VCC to ground.

The 163 counters count during half cycle of the 32 HZ timebase or during 1/64 seconds. The output of the counters is fed to a 373 latch. If, for example, the counter counts the 1 HZ during 1/64 sec, then the output of the latch should be 1000 / 64 = 15.6 as either 15 or 16.

The problem is that the count, which I verify by an oscilloscope at the output of the latch, is not correct and the problem could be metastability which was not resolved with two D flip-flops is series.

Here are some examples:

Clock = I HZ, output of the latch is 00011111 which is double of 00001000.

Clock = 2 KHZ, output is 00111111 which corresponds to 4 KHZ.

Clock = 2.4 KHZ, output is 00100111 which corresponds to 2.96 KHZ.

Clock = 3 KHZ, output is 00101111 which corresponds to 3.008 KHZ and is acceptable.

Clock = 4 KHZ, output is 00111111 which corresponds to 4.032 KHZ .

Clock = 4.6 KHZ, output is 01001010 which corresponds to 4.736 KHZ .

Clock = 5 KHZ, output is 01001111 which corresponds to 5.056 KHZ .

Clock = 8 KHZ, output is 01111111 which corresponds to 8.128 KHZ .

Clock = 9 KHZ, output is 10001111 which corresponds to 9.344 KHZ .

Clock = 10 KHZ, output is 10011010 which corresponds to 9.856 KHZ .

I am particularly concerned with when the error at the output of latch is more than 65 HZ.

I use pulse generator of my oscilloscope for generating the input clock frequency to the 163 counters.

When I use output of Qf (1 KHZ) of the 4040 of the timebase generator as input clock from the 163 counters and the same two AND gates and inverters to generate the update and reset pulses, I do get the correct count at the output of the latch. This reveals the timing issue for getting the right count of an external frequency. So, how can we correctly read (sample) an external clock frequency that comes from a source other than the 4040?

The actual connection of counters and latch is as shown in the original schematics. I included the timebase generator, the gates, part numbers, and a picture of the oscilloscope. I had taken the pictures when I was testing 16 HZ timebase with similar results. I had two probes but unfortunately one of my probes is now defective so I could not show the pulses on one screen when I took the new picture with 32 HZ. I hope this can help. When I used a low pass filter of 100 KHZ all outputs of the latch went high. So I eliminated the filter from the circuit.

Could someone who is well experienced with frequency sampling tell me why the count is wrong specially when the count is double?

I appreciate your response and thank you.

Are you keeping to the rise and fall times required for the 74HC163 counters? The voltage seems to be about 4.5 V, and this data sheet https://assets.nexperia.com/documents/data-sheet/74HC_HCT163.pdf says that the inputs should change at 139 ns/V or faster.

The input is likely to change by about 4 V, so including both rise and fall, the maximum time for transitions up and down is 1112 ns, or about 1 μs. At 1 kHz, the period is 1000 μs, so the waveform has to be high or low for 99.9% of the time, and only going up or down for 0.1% of the time or less. This means that anything that isn't a really sharp rectangular wave will not be counted correctly.

If you have a sine wave or anything with a slow rise or fall, I suggest you square it up with a schmitt trigger gate first.

Thank you for your reply.
I had tried the circuit also with 6 volts but the result was not changed.
My mini oscilloscope shows that the pulses are perfectly squared as you can see from thee attachment.
At 1 KHz and 2 KHz, the count is double. At other frequencies there is smaller error as you can see from my description.

The double count makes me think that the counters are being triggered on the falling edge of the waveform as well as the rising edge.

I can't see if the pulses are sharp enough from the oscilloscope. The images are a bit blurry so the numbers aren't clear, but more importantly it's not possible to see 0. 5 μs rising and falling edges on an oscilloscope that is set to what looks like 20 ms per division. A really slow edge at 200 μs, which would be far slower than is specified for the counters, would still be a hundredth of a division. That is far beyond what any oscilloscope can show, because of the screen resolution and what can be seen by the human eye.

You need to zoom right in so that there rise time or fall time can be seen. You will need to trigger the oscilloscope separately for rising and falling edges.

If your oscilloscope has a bandwidth of 10 MHz, then it probably can't show an edge that is changing at 139 ns/V, but if the edge is changing faster than a 10 MHz bandwidth can measure, the edge is probably fast enough.

1- I took new pictures of the scope when testing TB, UPD and RST = 32 Hz.

I see the following numbers:

For the TB: Vp-p: +44.8v Vp-p: +20.0 mV Freq: 32 Hz

For the UPD: Vp-p: +46.4 Vp-p: +20.0 mV Freq: 32 Hz

For the RST: Vp-p: +45.6v Vp-p: +40.0 mV Freq: 32 Hz

2- Someone commented that if I use 74VHC4040 instead of the 74HC4040 I get better results but the problem will remain. What do you think about that?

3- An example of 74VHC4040 is part n umber TC74VHC4040FK which comes in REEL package. I don’t know if there is a socket adapter to use it as through hole IC on breadboard. Do you think it would be possible to adapt the IC to be usable on the breadboard?

Thank you

Try feeding the input signal though a schmitt trigger gate, to ensure the input to the counters is a "clean" logic level signal.

I had already tested that. Unfortunately it did not help. Also when I used a 100 KHz low pass filter, the result was worse as there was logic high at all outputs of the register With 1 KHz frequency as input clock for the counters.

Do you have decoupling capacitors across all devices? Typically 10nF to 100nF ceramic.

These need to be as close as possible to each chips power supply pins.

Solderless breadboards have relatively high interconnect resistance and impedance. Failure to properly decouple each chips power supply pins can cause issues that can result in missing and/or extra pulses.

Yes I have 10 nF capacitor grounded from VCC Pin of each of the ICS. I also mentioned that in my description of the problem Although I did not mention the 10 nF.

Try looking at the waveform given by the scope pulse generator with that connected to the input, whilst displaying & syncing to the count enable signal at the same time, with that expanded to full screen width.

It should be possible to see and count the input cycles.

Cable said:

I had already tested that.

Click to expand...

Are you referring to a Schmitt-trigger input?
If so, what gate did you use for the Schmitt-trigger?

crustchow Sorry I missed your reply. Yes I meant the schmitt-trigger part number SN74HC14N. The attached image shows the outputs of the schmitt-trigger when the two input frequencies are fed to the schmitt-trigger.

rjenkinsgb Sorry. I dont know what do you mean by " whilst displaying & syncing to the count enable signal ".

Cable said:

@rjenkinsgb Sorry. I dont know what do you mean by " whilst displaying & syncing to the count enable signal ".

Click to expand...

Your scope is dual (or more) trace.

Use one input on the count enable and sync the scope to that, so a single "enable" level is filling a good part of the display.

Then connect the other scope input to the scope signal generator whilst that is connected to the counter clock, so the number and shape of pulses or cycles can be seen.

That allows the real count input to be compared to what is is displayed.

Thank you for trying to help me with the counting issues. I realized that my problem was the timing of upd and reset pulses. When I created a space between the reset and rising edge of TB, the count seems to be ok except that the count varies by one or two with different input frequencies to the counter. I found an interesting link https://www.planetanalog.com/metastability-in-space/# that explains that metastability (as I mentioned before in this post) events are common in digital circuits and can have negative effects.

The link shows a diagram of a design to solve the problem. Unfortunately, wit my limited knowledge, I have some confusion with the pin connections in the design of the presented link. Would you be able to clarify each of the following points for me from the design diagram of the link?

1- As I understand, this design should help to synchronize the count of different asynchronous input frequencies to my counters (which are timed by the TB of my schematics) so that the input frequencies are passed through the two flip-flops of the design and then feed the counters to count correctly. Am I right about that?

2- In the diagram of the design of the link, the clk pins of the two flip-flops are connected to “reset from clock tree”. What is the “reset from clock tree”? where should I connect the clk pins of the two flip-flops when I do not have clock tree (I do have two separate counters working with the TB)?

3- The diagram shows that the input clock pulses (which correspond to the TB pulses of my schematics) are connected to a triangle on the flip-flops. Which pins of the flip-flops the triangles represent? I need to know to which pin of the flip-flops should I connect the clock (TB) pulses?

I really appreciate your helpful answer.

Look at page 207.

GATE SYNCHRONIZER

Synchronizers in general are a way of aligning random outside-world
commands and then getting them to exactly fit a time slot in a timing
system.

Click to expand...

A old counter design of mine that used a gate synchronizer circuit from the TTLCB.

Thanks. I appreciate the link you sent to me. However, the page 207 of the book shows how to cascade flop-flops. The link I talked about shows a specific diagram that is does not seem to be exactly cascaded flop-flops (or am I wrong about that?). I need a response for the 3 points I mentioned. Has anybody an answer to those three points?

Cable said:

Thanks. I appreciate the link you sent to me. However, the page 207 of the book shows how to cascade flop-flops. The link I talked about shows a specific diagram that is does not seem to be exactly cascaded flop-flops (or am I wrong about that?). I need a response for the 3 points I mentioned. Has anybody an answer to those three points?

Click to expand...

For point
#1.
Read the entire chapter and eventually the entire book so you understand Digital Synchronizer theory. Then the connections will easily become apparent.

For point 2&3 you need to look at the patent data for specifics. It seems overly complicated for a simple digital counter.

I don’t know why it did not occur to my mind to do that search.
Thanks a lot for your reply.

Hello:

In the second schematics which I included with my original post, I showed a latch sn74HC373. Do you know if there would be any conflict between the ICs if I use a faster CD74AC373E instead of the sn74HC373 when the counter ICs remain the sn74HC163?

Thank you

I got my answer here: