It could be improved in many ways besides BJT, missing details, minimal line paths, but the concept of fill factor, font,/ trace size, symbols dots, redundancy reduction makes it very easy on the eyes. But then this is only a conceptual schematic unlike professional standards.Is Fig1 supposed to be an example of a bad schematic? Q1 has no emitter/collector distinction.
It could be improved in many ways besides BJT, missing details, minimal line paths, but the concept of fill factor, font,/ trace size, symbols dots, redundancy reduction makes it very easy on the eyes. But then this is only a conceptual schematic unlike professional standards.
I think it could be done is about 10 minutes.They probably paid at least few hundred dollars for that drawing
I never use Adobe but it is very secure with the proper setup. I use Foxit or Sumatra with Firewall blocked .Few years ago, I've got a virus through Adobe Acrobat Reader which automatically opens PDFs. Had to rebuild the computer. Took me few days. I don't use Adobe any more. I now save PDFs and watch them with off-line reader. I have quite a collection
I think it could be done is about 10 minutes.
Hi,
I found a flaw in the 'corrected' drawing in post #1. This is a minor point, but a point nonetheless.
If you look at Item #3, it shows a transistor circuit not draw well at all. If you look at the 'corrected' drawing it is better, but not quite up to par. Notice the dots on the base connections and the collector connections. We could have draw these two with two less dots, by combining the connection points for the upper base resistor and output collector terminal connection.
This kind of thing should also be avoided. So i guess the rule here is, "Minimize the number of dots for connections when possible".
When i saw that thread again (after seeing the thread had been moved) i saw that drawing first before the one before it, and thought that was going to be an example of using too many dots in a schematic drawing but lo and behold it was the 'corrected' one (har har)
Not bad, but not as professional as it could be.
I nearly always create schematics with LTspice. The chip symbols in the standard libraries don't usually have such conveniently-positioned pins. It would be a major effort to convert the symbols and a major inconvenience to have to use alternative drawing software.3) Chips should be depicted using pin positions that best prevent crossing wires.
My concern with that would be at 4-way junctions. We should try to avoid 4-way junctions whenever possible, and while only one dot would be needed, for clarity sake we should jog one of the wires over and add a second dot. Below is an example:
View attachment 93018
The above should generally be avoided, as it may be difficult to see the dot and one might assume the wires do not connect. Or, perhaps, they are simply crossing over one another and someone assumes the above is true (they are connected). Instead, this type of 4-way junction should be drawn as follows:
View attachment 93019
This eliminates all doubt that the top wire and bottom wire are connected to the horizontal one. However, it has two dots rather than one.
I understand where you're coming from, but I feel it should be reworded. Otherwise it could be more confusing.
Jogging the dots just makes the connections seem to be required to be near a certain component
I agreee about 4-way connections. They're quite common, and I don't remember ever missing a dot. The suggested alternative looks messier.
DerStrom8 said:Another point that I don't think he made, in schematics wires should ALWAYS go either left, right, up, or down. When people draw schematics with wires going off at angles it makes it very sloppy and difficult to follow. The only exception I can think of is in a bridge rectifier schematic, but even then I would prefer that it be redrawn to be either vertical or horizontal.
I came across an old Protel drawing at work where the dots had faded, and the other engineers and I were struggling to determine which were connected and which weren't. It would have been far easier if they had been jogged, whether the connection dots were visible or not.
I thought i made it clear with the couple of examples but let me expound this a little more.Not quite sure I'm following...?
I came across an old Protel drawing at work where the dots had faded, and the other engineers and I were struggling to determine which were connected and which weren't. It would have been far easier if they had been jogged, whether the connection dots were visible or not.
Dots cannot fade in the schematics posted to the forum!
I thought i made it clear with the couple of examples but let me expound this a little more.
Well, take the number of drawings you could not read and divide by the number of drawings that you could read plus the number you could not read, and then multiply by 100. That will give you the percentage of drawings that you could not read over your lifetime so far:
PercentCouldNotRead=NumberCouldNotRead/(NumberCouldRead+NumberCouldNotRead)
I think that will put the problem is a more balanced light, but please read the third point next...
This also brings up a third point about the connections. A convention we always used back in the day was to draw a small "half circle" to sort of "jump" over the line when there was no connection. This would mean that any connection that was not really a connection would cross the other non connected line with a half circle rather than just a straight line crossing another straight line.
. A convention we always used back in the day was to draw a small "half circle" to sort of "jump" over the line when there was no connection. This would mean that any connection that was not really a connection would cross the other non connected line with a half circle rather than just a straight line crossing another straight line.
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