ESPESP32-PICO-V3-02

[HelitAbasia]

Hello, I wanted to design a watchdog circuit for ESP-32.which can wait 15 minutes before sending RESET pulse to ESP-32.can anybody suggest me how can I do That?

 

[ahsrabrifat]

You can design a watchdog timer circuit for the ESP32 that waits 15 minutes before resetting the ESP32 using a 555 timer, a microcontroller, or a watchdog timer IC.

You can configure 555 as a monostable multivibrator to generate a reset pulse after 15 minutes.

A small microcontroller like ATtiny85 or an Arduino Nano can act as a watchdog. The ESP32 must periodically send a signal (e.g., HIGH pulse every few seconds). If no signal is received for 15 minutes, the ATtiny85 will pull the ESP32 reset pin LOW.
If you don't wanna use a microcontroller, you can use a low-power watchdog timer IC like TPL5010 or MAX6369 instead. If you want to make a PCB for your system, here you can get some idea about the cost.

ALLPCB.com

ALLPCB.com

www.allpcb.com

 

[danadak]

You can always use ESP32 to trigger its own reset with its WDT OR

But for external use an ATTINY85 and mBlock (to code) -

Note if you wanted to trigger the reset off a pin state or pulse width or V level or frequency thats
also trivial to do using block programming. Or use a combo of time and these other triggers.

Also you could easily add a check by this solution that ESP32 indeed did get reset, otherwise issue
another reset. Redundancy.....reliability.....have ESP32 set a pin or gen a V for pulser to confirm....

mBlock takes block code and converts to Arduino code as seen in right hand window. Use a Nano
or UNO board and Arduino, setup Nano/UNO as ISP, and program the Attiny85 with that.

A couple of more block type solutions for future consideration on other applications -

Pulse Sequence Generator / Smart Timer

Often users, developers, hobbyists need timed and qualified event generators, many resorting to 555 timers and the like. The venerable 555 has had a long run but its limited in accuracy and capability. This approach uses block language to create...

www.electro-tech-online.com

GUI Codeless Processor Design

Micro design has for years relied on ASM and C programming and other languages. Often many tasks are fairly simply but these tools were focused and quite a learning curve, especially ASM and C and C++. There are a number of new GUI based tools that essentially take out the "strong typing"...

www.edaboard.com

 

[ZipZapOuch]

Hello, I wanted to design a watchdog circuit for ESP-32.which can wait 15 minutes before sending RESET pulse to ESP-32.can anybody suggest me how can I do That?

Everything you need to put the ESP32 into deep sleep or wake from deep sleep at a given time can be done in software. Don't use the watchdog timers, use the dedicated wake and sleep functions. The WDTs are intended as watchdogs and better suited for monitoring the time certain processes take.

Here is a tutorial for wake and sleep...

ESP32 Timer Wake Up from Deep Sleep | Random Nerd Tutorials

This tutorial shows how to put the ESP32 in deep sleep mode and wake it up with a timer after a predetermined amount of time. The ESP32 will be programmed with Arduino IDE.

randomnerdtutorials.com

 

[danadak]

What is the goal of reset to :

1) Reliability in case ESP32 "loses" its way in code execution ?
2) Simple re-initialization of ESP32 to restart from a known state ?
3) Wakeup ESP32 (your having put it to sleep at some time prior) ?

What is the reason for doing this periodic reset ?

Note the timers are 64 bit, with an 80 Mhz clock (or lower one)
producing resets low period timing trivial.

Many ESP32 versions dual core, so if a reliability issue one can consider one
core checking on the other....not perfect as they share a lot of the same HW
and internal logic/busses, but a possibility.

If reliability is prima facie consideration processors with traps would offer
more protection (chatGPT response) :
****************************************************************************************************************
Address traps are a feature used by some microprocessors, typically for debugging or managing memory access violations. When an address trap occurs, the processor triggers an exception or interrupt when certain addresses are accessed, which helps with tasks like memory protection, access control, or debugging.


As of 2025, here are a few microprocessors and architectures that implement address traps or similar mechanisms:

1. ARM (Various Models)​

• ARMv7 and ARMv8 (e.g., Cortex-A series): These processors support a variety of exception mechanisms that include address traps for memory access violations. Features like Memory Protection Unit (MPU) or Memory Management Unit (MMU) in ARM cores can be used to trap certain memory accesses (such as illegal memory regions or access to non-cacheable regions).
• TrustZone: ARM TrustZone also allows trapping access to sensitive memory regions for secure execution environments.

2. x86 and x64 (Intel and AMD Processors)​

• Intel: Modern Intel processors, especially those with Intel VT-x (Virtualization Technology), include mechanisms like page faults, segment faults, and access violations, which can be considered a form of address trap. Additionally, Intel's Memory Protection Extensions (MPX) offer further control over memory access, although MPX has been deprecated in recent Intel processors.
• AMD: AMD processors also support similar features for trapping memory violations, including page faults, data access faults, and virtual memory protections.

3. RISC-V​

• RISC-V: The RISC-V architecture supports address traps through its page faults and access violations mechanisms. RISC-V also provides support for memory protection and privilege levels to control access to certain regions of memory, triggering exceptions when violations occur.

4. MIPS​

• MIPS processors: The MIPS architecture has provisions for trapping memory access violations using TLB (Translation Lookaside Buffer) exceptions and address exceptions. These exceptions are triggered when a program accesses a restricted or invalid memory address.

5. PowerPC​

• PowerPC (e.g., IBM Power Series): PowerPC processors feature address traps as part of their memory management unit (MMU). These traps are typically used for address translation errors or protection faults when a program accesses restricted or invalid memory locations.

6. SPARC​

• SPARC processors (e.g., Oracle's SPARC series): SPARC processors implement address traps using mechanisms like page fault traps and memory protection exceptions.

7. Custom Embedded Processors​

• Some custom or embedded processors may include specific address trap mechanisms in their memory management units (MMUs) or as part of custom debugging and protection features. For example, microcontrollers with MMUs might be able to trap invalid or unauthorized memory accesses as part of their system design.

Common Mechanisms Involving Address Traps:​

• Page Faults: Triggered when an illegal memory access is attempted.
• Memory Protection: Systems can trap accesses to memory areas that are marked as read-only or otherwise restricted.
• Access Violations: Trap illegal operations like executing data or reading/writing to non-permitted regions.

While not all processors explicitly label their features as "address traps," many modern processors provide mechanisms for trapping illegal memory accesses, which achieves similar results. These features are particularly useful in operating systems, debuggers, and security contexts.