hi eng,
The 'noise' in the system is not related to the 'internal offset voltage'.
The 'internal offset' is due to the opa's internal operation.
Other zero offset errors can be caused by component matching differences or errors due to the bridge voltage output not being zero without any load applied.
All the load cells I have used have this zero offset.
The 'zero errors' can be reduced by applying a voltage to a summing junction on an opa input.
I would suggest using U3A +inp as the summing junction.
From a stable voltage source connect a variable resistor to 0V, from the wiper of the variable connect a resistor to U3A+inp.
Chose the polarity of the stable voltage such that it will cancel out the zero offset. [offset could be +V or -V]
Noise sources can internally generated from your system or from external sources.
There are many potential sources of 'internal' noise.
Power supplies, poor decoupling, incorrect grounding, lack of screening, etc
As your load cells outputs are in the range of about 0mV thru 10/20mVolts,its important that you minimise the noise
before you amplify it and connect to the ADC.
I would recommend that you look at the www.analog.com site for applications data regarding 'noise'.
edit: application notes AN244 and AN106 as a starter.
What gain are you expecting from the amplifier in your drawing?
Is the 1K0 feedback resistor across the U3A a misprint ?.
If not check the CMR data, because the resistor from the +inp to ground ref is 10K0
EricG
This is only a brief/crude description of noise and offsets, read the reference material from analog and others for more details.
The 'noise' in the system is not related to the 'internal offset voltage'.
The 'internal offset' is due to the opa's internal operation.
Other zero offset errors can be caused by component matching differences or errors due to the bridge voltage output not being zero without any load applied.
All the load cells I have used have this zero offset.
The 'zero errors' can be reduced by applying a voltage to a summing junction on an opa input.
I would suggest using U3A +inp as the summing junction.
From a stable voltage source connect a variable resistor to 0V, from the wiper of the variable connect a resistor to U3A+inp.
Chose the polarity of the stable voltage such that it will cancel out the zero offset. [offset could be +V or -V]
Noise sources can internally generated from your system or from external sources.
There are many potential sources of 'internal' noise.
Power supplies, poor decoupling, incorrect grounding, lack of screening, etc
As your load cells outputs are in the range of about 0mV thru 10/20mVolts,its important that you minimise the noise
before you amplify it and connect to the ADC.
I would recommend that you look at the www.analog.com site for applications data regarding 'noise'.
edit: application notes AN244 and AN106 as a starter.
What gain are you expecting from the amplifier in your drawing?
Is the 1K0 feedback resistor across the U3A a misprint ?.
If not check the CMR data, because the resistor from the +inp to ground ref is 10K0
EricG
This is only a brief/crude description of noise and offsets, read the reference material from analog and others for more details.
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