With those circuits you are playing with SET and PRESET inputs, they override the output and the clock, acting like a R-S latch
Have another look at the circuit. It's not latching.
Again, you are latching them, every time you play with asynchronous SET, RESET, PRESET, you override the F/F with a latch. (usually SR).
The both ICs are D Flip Flops.
Pin 6 from 4013 is the PRESET input. (You latch.) -> The F/F starts cleared, due the RESET pin being pulled
up, then when you press the button, the PRESET sets the output, after you release the button, the RESET pin clears the output again.
(Typical SR latch working, you are just using SR latch inside it).
Pin 4 friom 7474 is the PRESET input (You latch.) -> The F/F starts cleared, due the RESET pin being pulled
down, then when you press the button, the PRESET sets the output, after you release the button, the RESET pin clears the output again.
(Typical #S#R latch working, you are just using the #S#R latch inside it).
You can see that you need to ground the CLOCK and D inputs, so that any voltage pertubations at them could change the output.