JK FLIP FLOPS

[sxy]

HI

Figure A of Question 6 shows a diagram of a circuit made up of JK FLIP FLOPS components, which respond to the
.decrease of each CLOCK

For the SI input, the DATA information signal, shown in Figure B, is provided .
Assume that at time T = 0
Q1 = Q2 = Q3=0.
A. Indicate the purpose of the circuit shown in Figure A.(In the file attached).
B. Indicate a possible use of the circuit shown in Figure A.
Thanks a lot

 

[rjenkinsgb]

The purpose is a "shift register" as I've said several times.

Just remember that each flip flop takes the state of its input after the clock edge occurs (if the input has changed since the previous clock).

Draw the waveforms initially (for your own use) with an obvious visible delay from the clock to the output following any change, eg 1/4 clock cycle; that will make it easier to see the sequence effect and how each stage affects the next.

 

[sxy]

Figure A of Question 12 shows a diagram of a circuit made up of type D FLIP FLOP, which respond to the increase of each
Clock pulse (CLOCK.) The clock pulses are shown in Figure B of the question.
Before the first clock rose, the findings were as follows:
Q2 = 1; Q1 = 0; Q0 = 0.

A. Copy to your notebook the clock pulses in Figure B, and draw below them, one below the other, respectively,
The waveform at each of the outputs Q2, Q1, Q0 for the three clock pulses.
B. Write the output state Q2, Q1, Q0 after three clock pulses.
C. Mention the use of the circuit described in Figure A for the question.

 

[rjenkinsgb]

See my last answer.

The reason I use the term "Clock edge" is there are types that are triggered by a positive edge, as well as the negative edge triggered ones you showed before.
(There are also types where the inputs are stored on one clock edge then transferred to the output on the opposite edge).

No one is just going to answer your homework questions for you; you need to try yourself, then if you don't understand something and the answer is not quite right, we will try and help you to understand so you do get the right answers.

 

[sxy]

Question 4
A. Figure A for question 4 describes the logic circuit of a synchronous SR flip-flop, which is controlled by input-enable E.

Below is a table containing the input and output states of a FLIP FLOP. Copy the table into your notebook and complete it.


B. In the logic circuit from section A, changes were introduced, and a different type of FLIP FLOP was obtained, described in Figure B for the question.

1. Copy the table below into your notebook and complete it.

2. What type of FLIP FLOP is described in Figure B for the question? Justify your answer.

 

[sxy]

I thought that the ansewt to B is T-flip flop.
Am I right?
Thanks a lot.

 

[rjenkinsgb]

I thought that the ansewt to B is T-flip flop.
Am I right?

No. T is "Toggle", a single stage that toggles if the control input is high or holds with it low.

The type is in the pdf title; (S-R; Set-Reset)

The second is still a type of S-R, but not one I have a specific name for.
It is not self-toggling, it will follow the data input.

It's possibly a gated D type., though D types are normally edge triggered.

Really, I'd class it as a single bit "transparent latch".

See the function table for a 74LS373:

https://www.ti.com/lit/ds/symlink/sn54ls373-sp.pdf?ts=1658603287820

 

[sxy]

Thanks for your answer.
But you can see in table b that when E=1 and A=1 then QN=0
so It could be T-FLIP FLOP; because if it is a D-FLIP FLOP then A should equal to QN.
Thanks a lot.

 

[rjenkinsgb]

so It could be T-FLIP FLOP; because if it is a D-FLIP FLOP then A should equal to QN.

No.
A T type toggles at each clock cycle with a fixed high data or control input.

That circuit is still the SR above, just with the inputs fixed to always be opposite each other.
It will always has the same output for the same input state - NO toggle.

It appears the drawing has errors, and messing up the truth table?

The circuit is identical to the SR above, other than the addition of the inverter between the inputs - but S and R are swapped, with Q and /Q still the same, which is impossible.

They should be the other way around, or re-labelled.

I'm guessing the A input should have been the lower one (S) and feeding out to the upper R input of the original circuit.

Either that or it's a very badly created attempt to confuse students and ensure they are looking at details.

 

[sxy]

Figure A of Question 12 shows a diagram of a circuit made up of type D FLIP FLOP, which respond to the increase of each
Clock pulse (CLOCK.) The clock pulses are shown in Figure B of the question.
Before the first clock rose, the findings were as follows:
Q2 = 1; Q1 = 0; Q0 = 0.

A. Copy to your notebook the clock pulses in Figure B, and draw below them, one below the other, respectively,
The waveform at each of the outputs Q2, Q1, Q0 for the three clock pulses.
B. Write the output state Q2, Q1, Q0 after three clock pulses.
C. Mention the use of the circuit described in Figure A for the question.