FPGA Circuits?

dknguyen said:

Then use an FPGA module like micronova mercury (uses outdated software but easier to get started) or Trenz 0714 (more powerful and up to date). FPGAS are a PITA and expensive to design and make boards for.

you'll need to learn vhdl or verilog.

Click to expand...

Robo_Pi said:

I already have an FPGA developement board and I'm currently learning VHDL. I also already have experience designing digital logic circuits.

All I'm interested in here is finding an extremely simple example of a neural network for an FPGA. I need something extremely simple. Something designed for teaching the concept. I don't want a large neural network that has already been programmed into a library. That won't do me any good. I want to understand how to build a neural network on a FPGA from the ground up. So I'm looking for the simplest possible example circuit. Kind of like the "Hello World" for Neural Networks on an FPGA.

Click to expand...

dknguyen said:

ah, i see. outta my league then.
**broken link removed**

http://stackoverflow.com/questions/2190470/neural-network-simulator-in-fpga
"Most attempts at building a 'literal' neural network on an FPGA hit the routing limits very quickly, you might get a few hundred cells before P&R pulls takes longer to finish than your problem is worth waiting for. Most of the research into NN & FPGA takes this approach, concentrating on a minimal 'node' implementation and suggesting scaling is now trivial.

The way to make a reasonably sized neural network actually work is to use the FPGA to build a dedicated neural-network number crunching machine. Get your initial node values in a memory chip, have a second memory chip for your next timestamp results, and a third area to store your connectivity weights. Pump the node values and connection data through using techniques to keep the memory buses saturated (order node loads by CAS line, read-ahead using pipelines). It will take a large number of passes over the previous dataset as you pair off weights with previous values, run them through DSP MAC units to evaluate the new node weights, then push out to the result memory area once all connections evaluated. Once you have a whole timestep finished, reverse the direction of flow so the next timestep writes back to the original storage area."

Click to expand...