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Freq divider by 4?

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electroRF

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Hi,
I was reading this slide, and saw how they divide frequency by 4, which seems wrong to me.

Why did they connect Q1' with Q0'?

Does that make sense to you?

(Slide is from https://www.slideshare.net/DeepakFloria/divide-by-n-clock)

Thank you.
dff.jpg
 
No, just more crap posted on the internet by some "expert". Leave out the wire from Q0' to d0, and it becomes a Gray code counter with four states which will divide by four.
 
Er!!! No the second D type should be clocked by the first.. The way they have it Q1', Q0' and D0 will fry!!

No, if you do it like I said, it is a synchronous counter with the external clock going to both Clk inputs. The way Ian suggests turns it into a ripple counter, with its usual hazard problems.

DF28b.jpg
 
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No, if you do it like I said, it is a synchronous counter with the external clock going to both Clk inputs. The way Ian suggests turns it into a ripple counter, with its usual hazard problems.
I tried it your way, I doesn't divide by four.... The ripple counter does.... Anywho the OP was right!!! doesn't work as shown!!

Opps!! Sorry Mike you are correct.... Just tried it again...
 
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As you can see in the sim above, the Gray Code counter counts 01320132... The two outputs are in phase quadrature.
 
A "divider" is nothing but a counter. A counter is just a state machine. I learned how to design state machines long before I even heard of dividers. Your reference just muddies the water by talking about designing dividers as though it is a whole new discipline...
 
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