M mjunaid61 New Member Oct 18, 2011 #1 Hi, I have a frequency of 25MHz and I want to decrease it to 11MHz using FPGA . the ratio between the frequencies is 2.25 which will generate 11.11 MHz. The question is how to divide 25MHz by a factor of 2.25 Any help will be appreciated Thanks
Hi, I have a frequency of 25MHz and I want to decrease it to 11MHz using FPGA . the ratio between the frequencies is 2.25 which will generate 11.11 MHz. The question is how to divide 25MHz by a factor of 2.25 Any help will be appreciated Thanks
B BrownOut Banned Oct 18, 2011 #2 You have to multiply by 4/9. It can only be done by using a PLL to multiply the base frequency by 4, then you use a divider chain to divide by 9.
You have to multiply by 4/9. It can only be done by using a PLL to multiply the base frequency by 4, then you use a divider chain to divide by 9.
D Diver300 Well-Known Member Most Helpful Member Oct 18, 2011 #3 You could use a DDS chip. An AD9832 would probably work.