I am trying to understand the behaviours I am seeing when using an AD652 in the FVC mode (shown below).
View attachment 136716
(
https://www.analog.com/media/en/technical-documentation/data-sheets/ad652.pdf)
I conducted a series of measurements of the output voltage (Vout) across a wide range of input frequencies (each of which was held constant for the duration of the measurement) and found that Vout experienced instabilities (fluctuating periodically) at particular frequencies that coincided with multiples of the clock frequency (2.5MHz). I'll attach my graphs below.
I have set up an LTSpice simulation but am having difficulty reproducing the circuit.
View attachment 136721
I'd appreciate any help in fixing my simulation and understanding what components of the circuit give rise to the instabilities in the Vout - Fin graphs.
The following graph shows the residuals associated with the linearity of the positive and negative slopes. The residuals of the negative slopes are usually 3 orders of magnitude greater than those of the positive slopes:
View attachment 136717
This is an additional graph I made, showing the relationship of the input frequencies relative to the clock frequency (25MHz):