help on vhdl

[abilash]

hello, i am doing a project in vhdl. i have a probem. i am using if else statement. i am required to exit from the program when if condition is satisfied. how can it be done. it is as illustarted below
eg:

if( a='0') then
.
.
.
.
exit; <---- i need to exit from the loop here...

else

.
.
.
.
.

end if;

 

[abilash]

is there any provision for indirect access such as pointers in c... i am having a set of memory locations... i need to read data from one of the memeory locations specified.... how can it be done in vhdl....

please help me out with this...
with regards....

 

[Optikon]

hello, i am doing a project in vhdl. i have a probem. i am using if else statement. i am required to exit from the program when if condition is satisfied. how can it be done. it is as illustarted below
eg:

if( a='0') then
.
.
.
.
exit; <---- i need to exit from the loop here...

else

.
.
.
.
.

end if;

First of all, what you show is NOT a loop. an if-then-else statement is NOT a loop. VHDL is a hardware description language. The if-then-else statements builds logic in hardware - there is no loop.

When you say "exit" that is very ill defined. You normally set some other condition inside the "if" statement that is examined elsewhere .

If you think of VHDL with a C-programming mindset, you will have much trouble.

 

[abilash]

sir, do u mean if statement is not a loop... if so how can i achieve exit from that condtion... is there any thing such as goto last so that i can exit from the program... please suggest any i way i can achieve it...

thanxx

 

[Optikon]

sir, do u mean if statement is not a loop... if so how can i achieve exit from that condtion... is there any thing such as goto last so that i can exit from the program... please suggest any i way i can achieve it...

thanxx

The most proper way to have Hardware "loop" is with a state machine which uses flip flops triggered by a clock signal. Look up how to write state machines for VHDL. Again, I will tell you forget about thinking like a C programmer. VHDL builds hardware it is not instructions executed in a PC. There is no GOTO command nor should there be.

 

[abilash]

sir i am used to state machines... i know that.... it uses case statement... i feel my programming wont work with that. my code may run upto 2000 lines... when the reset condition is made low... it should make few signals low and exit from that.... if it is made high it should execulte all the rest of the 2000 lines program.... how can it be done...

i have a another requrement... can we implement any ting such as functions in vhdl... such as i have a case statement.. i'll check the bit patteren of a signal... depending on that the function shoulg be called... can v do that.. it is as illustrated..

case of ("value") =>

when 00 => function1 () <--- it should move to functon1 when value = 00
when 01 => function2 () <--- it should move to functon2 when value = 01
when 10 => function3 () <--- it should move to functon3 when value = 10
when 11 => exit; <--- exit from the loop


how can this be done.... please help me on this...
thaxx..
wit regards...

 

[tkbits]

You can write functions in VHDL (in a package).

There is only one problem.

Their only use in synthesis is to generate constant values. Under simulation (test bench), you can write typical "computer" code. Under synthesis, you are highly restricted in the code you can write.

So far, you have been using the fundamentals of software - sequences, iterations, and alternatives.

However, the fundamentals of sequential digital hardware are quite different. One possible set of fundamentals include: selection (multiplexing of several inputs into one output), distribution (connecting one output to one or more inputs), and updating (register clocking under control signals).

 

[srimannarayanakarthik]

sir i am used to state machines... i know that.... it uses case statement... i feel my programming wont work with that. my code may run upto 2000 lines... when the reset condition is made low... it should make few signals low and exit from that.... if it is made high it should execulte all the rest of the 2000 lines program.... how can it be done...


case of ("value") =>

when 00 => function1 () <--- it should move to functon1 when value = 00
when 01 => function2 () <--- it should move to functon2 when value = 01
when 10 => function3 () <--- it should move to functon3 when value = 10
when 11 => exit; <--- exit from the loop


how can this be done.... please help me on this...
thaxx..
wit regards...

How well versed are you in VHDl. have u heard of generics and generate. They are used to reduc the program cycle. search and vlsi site for generate example. you can eliminate the problem of lengthy code

 

[srimannarayanakarthik]

sir i am used to state machines... i know that.... it uses

case of ("value") =>

when 00 => function1 () <--- it should move to functon1 when value = 00
when 01 => function2 () <--- it should move to functon2 when value = 01
when 10 => function3 () <--- it should move to functon3 when value = 10
when 11 => exit; <--- exit from the loop


..
wit regards...

You can exit in this way. see in that case '11' in the above example you stated assign it to a signal let us say 'a'. Make it high when the condition is satisfied. Once the loop exits the control has to some loaction. You state that condition which has to be executed after the IF can condition is satisfied. Make a condition at that statement that only when 'a' is high that part of program is gonna execute

 

[Optikon]

sir i am used to state machines... i know that.... it uses case statement... i feel my programming wont work with that. my code may run upto 2000 lines... when the reset condition is made low... it should make few signals low and exit from that.... if it is made high it should execulte all the rest of the 2000 lines program.... how can it be done...

i have a another requrement... can we implement any ting such as functions in vhdl... such as i have a case statement.. i'll check the bit patteren of a signal... depending on that the function shoulg be called... can v do that.. it is as illustrated..

case of ("value") =>

when 00 => function1 () <--- it should move to functon1 when value = 00
when 01 => function2 () <--- it should move to functon2 when value = 01
when 10 => function3 () <--- it should move to functon3 when value = 10
when 11 => exit; <--- exit from the loop


how can this be done.... please help me on this...
thaxx..
wit regards...

you need to think about "exit program" differently. If your statemachine in VHDL can sense some exit "condition" then you can stop the advancing of states and maintain the current state forever.. this is "effectively" like exiting the program (it stops doing things!)

 

[abilash]

please tell me is there any statements which uses labels.... i may help me in jumping to various parts of the program so the function performance can be atchived. when some bit pattern is true i need to jump to some location mentioned by label... plz hep me on this...

thanxx

 

[abilash]

anybody plz help on this....

thanxx

 

[phalanx]

sir i am used to state machines... i know that.... it uses case statement... i feel my programming wont work with that. my code may run upto 2000 lines... when the reset condition is made low... it should make few signals low and exit from that.... if it is made high it should execulte all the rest of the 2000 lines program.... how can it be done...

You can not exit from a state machine. You can only switch to a different state. I don't know how you have your implementation broken up, but each entity in your design that is affected by the reset signal should have an input and the associated logic to make use of it. All components in your design would reset at the same time. It is critical that you understand you are not working in a linear algorithmic environment but an environment where parallelism and concurrency are the norm.

i have a another requrement... can we implement any ting such as functions in vhdl... such as i have a case statement.. i'll check the bit patteren of a signal... depending on that the function shoulg be called... can v do that.. it is as illustrated..

case of ("value") =>

when 00 => function1 () <--- it should move to functon1 when value = 00
when 01 => function2 () <--- it should move to functon2 when value = 01
when 10 => function3 () <--- it should move to functon3 when value = 10
when 11 => exit; <--- exit from the loop


how can this be done.... please help me on this...
thaxx..
wit regards...

You can not call functions in VHDL like you can in C. Your case statement should move a value into a signal that can be acted upon by other entities in your design which are "connected" to it.

please tell me is there any statements which uses labels.... i may help me in jumping to various parts of the program so the function performance can be atchived. when some bit pattern is true i need to jump to some location mentioned by label... plz hep me on this...

You have clearly not listened to any of the responses to your initial question. At a core logic level, there are no labels or functions that you can arbitrarily call or jump to. You can certainly implement an environment that would allow you to do so but that is far out of reach at the moment. You owe it to yourself to sit down and thoroughly read through a tutorial on VHDL meant for beginners. Here is a link to one that has helped friends of mine in the past as I'm not the best teacher on Earth. https://ece.gmu.edu/courses/ECE545/viewgraphs_F04/loCarb_VHDL_small.pdf

 

[gauravjindal]

hi.....
i want to do some project on vhdl but still not get thinking about latest project....

can u help me.and it should be latest and little complicated otherwise my teacher will rejected it....and

plz.....