Help! Verilog Decoder Simulation Issues

[wuchy143]

Hi All,

I have been able to write what I think is good code for a decoder which accepts in a 4 bit input and outputs a number up to 56818 depending on that input. I have a 50MHz clock. I wrote a testbench for it and it appears to work for the first two inputs then it just locks itself on the second input. Meaning the output stays at the second output for the rest of the simulation. Below is code and waveforms from Xilinx ISE. PLEASE HELP! Why is it getting locked like this?

Thanks


.v file:
`timescale 1ns / 1ps
module decoder(SW, CLK_50M, COUNT_VAL);
input wire [3:0] SW;
input wire CLK_50M;
output[15:0] COUNT_VAL;
reg [15:0] COUNT_VAL;


always @(posedge CLK_50M)
begin
COUNT_VAL = 0;
case(SW)
0000 : assign COUNT_VAL = 56818;
0001 : assign COUNT_VAL = 53629;
0010 : assign COUNT_VAL = 50619;
0011 : assign COUNT_VAL = 47778;
0100 : assign COUNT_VAL = 45097;
0101 : assign COUNT_VAL = 42566;
0110 : assign COUNT_VAL = 40177;
0111 : assign COUNT_VAL = 37922;
1000 : assign COUNT_VAL = 35793;
1001 : assign COUNT_VAL = 33784;
1010 : assign COUNT_VAL = 31888;
1011 : assign COUNT_VAL = 30098;
1100 : assign COUNT_VAL = 28409;
1101 : assign COUNT_VAL = 26815;
1110 : assign COUNT_VAL = 25310;
1111 : assign COUNT_VAL = 23889;
default : $display("Error");


endcase
end

endmodule



Testbench:

`timescale 1ns / 1ps



module decoder_testbench_v;

//declaring inputs/outputs
reg clk;
reg [3:0] s;
wire [15:0] out;


//generate free running clock 50MHz clock
always
begin
clk = 1'b1;
#10;
clk = 1'b0;
#10;
end

//instantiate my decoder
decoder(.SW(s),.CLK_50M(clk),.COUNT_VAL(out));

initial
begin

#100;

//test begins
s = 4'b0000;
#100;
s = 4'b0001;
#100;
s = 4'b0010;
#100;
s = 4'b0011;
#100;
s = 4'b0100;
#100;
s = 4'b0101;
#100;
s = 4'b0110;
#100;
s = 4'b0111;
#100;
s = 4'b1000;
#100;
s = 4'b1001;
#100;
s = 4'b1010;
#100;
s = 4'b1011;
#100;
s = 4'b1100;
#100;
s = 4'b1101;
#100;
s = 4'b1110;
#100;
s = 4'b1111;


end

endmodule






-mike