I'm dying to know what's in that file.
The .asc file is just a text file listing components/values/connections for the LTSpice simulation. Nothing exciting, and not needed if you don't use LTSpice.
Is it safe to assume that the three +12V "flags" go to the Vdd pins on the three ICs? Is it also safe to assume that it does not matter which "flag" goes to any given IC?
Correct. The flag just indicates 12V is present along the wire it's shown on.
Will the 40106 get hooked up like the last circuit? Moving from the flat side of the triangle to the circle at the point of the triangle 9-8, 1-2, 3-4. Bring 12V to pin 14 then ground all unused odd numbered pins?
You will only be using 2 (U1a, U1b) of the 6 inverters inside the IC. The symbol for an inverter is a triangle with a circle at one apex. The circle denotes inversion in any logic circuit and here is shown at the inverter output point. Let's say use pins 1 and 3 as inputs, pins 2 and 4 respectively as outputs. Pin 7 is grounded. Pin 14 is +12V. Ground unused input pins 5,9,11,13.
For the CD4093 it doesn't matter which of its four gates you regard as U2a, U2b etc; just remember your choice. Pins [1,2],[5,6],[8,9],[12,13] are inputs; pins 3,4,10,11 are outputs. Pin 7 is ground. Pin 14 is +12V.
I'm having a little bit of trouble finding a .33 uf cap for C10
Try 0.22uF or 0.47uF or anything close, and change R3 to 470k or 180k accordingly (better yet, make R3 a 500k trim-pot, which would allow adjustment of the 'flick' time).
It certainly would, but is OTT and may be more expensive.