I see from post 678 that we now know a bit more about the OEM controller wiring/control. Does it make use of pin 5 to shut the controller down?
I'm attaching drafts, for review, of a possible PDM-Mk3 using the 1084 suggested by ronv, and PDM-Mk4 using a (hopefully-rescued) 2576.
View attachment 65081View attachment 65082
Mk3 operation
The top half of the pic is a conventional linear v-reg using an LM1084 (U1) programmed for maximum output voltage by R1/R2. If FET M1 is turned on by control voltage Vt the v-reg turns on, powering the load (pump).
Load current is sensed by R9. Anything over ~2A turns on Q1, allowing C4 to charge negatively. If the C4 voltage reaches the lower Schmitt threshold of gate U2a the latch formed by U2a/U2b is tripped (set). This switches off the FET via D4, and also turns on Q2 via R7 to give an alarm output. The time before the latch trips is settable with the trimpot(~ 0.15-0.6 sec). A push-button allows the latch to be reset. R11/C6 provide power-on reset. R8/C5 provide a slow-start switch-on of M1 (albeit not very slow, to avoid significant FET heating). The 1084 needs a heat-sink to cope with ~1W during continuous running of the pump. R9 should be a wire-wound type (at least 1W rating). If a resettable fuse is used (type not yet determined) it could be thermally coupled to either U1 or M1 as a second line of defence.
Mk4 operation
Not having a Spice model of an LM2576 I used an LT1074 model with the shut-down logic inverted. The 1074 has internal limiting at 6A, similar to the 2576.
As for the Mk3, the LM2576 output is programmed for maximum output voltage. Since there is a shut-down input no external FET is needed to switch the v-reg on and off.
The current-sense and timed trip arrangement is similar to the Mk3, the difference being that U2a controls the v-reg shut-down. The current-sense resistor R3 needs to be placed such that the high ripple-current pulses through smoothing cap C2 don't affect the trip.
I'm attaching drafts, for review, of a possible PDM-Mk3 using the 1084 suggested by ronv, and PDM-Mk4 using a (hopefully-rescued) 2576.
View attachment 65081View attachment 65082
Mk3 operation
The top half of the pic is a conventional linear v-reg using an LM1084 (U1) programmed for maximum output voltage by R1/R2. If FET M1 is turned on by control voltage Vt the v-reg turns on, powering the load (pump).
Load current is sensed by R9. Anything over ~2A turns on Q1, allowing C4 to charge negatively. If the C4 voltage reaches the lower Schmitt threshold of gate U2a the latch formed by U2a/U2b is tripped (set). This switches off the FET via D4, and also turns on Q2 via R7 to give an alarm output. The time before the latch trips is settable with the trimpot(~ 0.15-0.6 sec). A push-button allows the latch to be reset. R11/C6 provide power-on reset. R8/C5 provide a slow-start switch-on of M1 (albeit not very slow, to avoid significant FET heating). The 1084 needs a heat-sink to cope with ~1W during continuous running of the pump. R9 should be a wire-wound type (at least 1W rating). If a resettable fuse is used (type not yet determined) it could be thermally coupled to either U1 or M1 as a second line of defence.
Mk4 operation
Not having a Spice model of an LM2576 I used an LT1074 model with the shut-down logic inverted. The 1074 has internal limiting at 6A, similar to the 2576.
As for the Mk3, the LM2576 output is programmed for maximum output voltage. Since there is a shut-down input no external FET is needed to switch the v-reg on and off.
The current-sense and timed trip arrangement is similar to the Mk3, the difference being that U2a controls the v-reg shut-down. The current-sense resistor R3 needs to be placed such that the high ripple-current pulses through smoothing cap C2 don't affect the trip.