That is a *lot* of parts. Please explain its operation.
Also . . .
Why is there a 1.4 kHz oscillator gated on and off at a 120 Hz rate, in the middle of a PFC circuit? Are you creating a delay by integrating cycles of an oscillator?
What is the purpose for D2?
Q1 applies a dead short to GND across the +5 V rail.
Delete R8.
Choose a different comparator and eliminate the 5 V supply, along with almost everything to the right of U2.
If you reverse the inputs to U2, you can eliminate Q13, R46, R47.
The M4 drain current is less than 60 mA. If you change M4 to a small logic-level FET, you can drive it directly with U2, and eliminate Q3, Q13, R8, R10, R45, R46, R47, R48. If you run the entire circuit on 12 V, M4 could be something simple like a 2N7000/7002.
Connect the U2 and U5 non-inverting inputs together, and delete R6, R7, C4.
There is no base current limiting for Q14.
You have two bridge rectifier circuits essentially in parallel. Connect the D14-D16-C10 node to the R9-C15 node through D21, and eliminate D22, D23, D24.
Why not put R29 in series with D18? It would switch off itself when the boost converter kicks in.
What is the discharge path for C9?
C10 degrades the effectiveness of the PFC stage. What is its purpose?
Delete R40 or R41.
What is the purpose of R48?
There is no capacitance in the Q11 base circuit, so Q8 is constantly applying discharge pulses to C3 at a 120 Hz rate.
I think U1, U5, and almost everything around them can be replaced with a simple R-C ramp going into U2.
ak