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L1 will short the gate to ground for DC, but that is fine. Q1 is a JFET that work when the gate is negative compared to the source and the drain is positive compared to the source.
This circuit gets those voltages correct.
At the transmitting frequency, L1 is tuned with C1 (mainly) so the impedance to the desired frequency is quite high.
L1 will short the gate to ground for DC, but that is fine. Q1 is a JFET that work when the gate is negative compared to the source and the drain is positive compared to the source.
This circuit gets those voltages correct.
At the transmitting frequency, L1 is tuned with C1 (mainly) so the impedance to the desired frequency is quite high.
L1 will short the gate to ground for DC, but that is fine. Q1 is a JFET that work when the gate is negative compared to the source and the drain is positive compared to the source.
This circuit gets those voltages correct.
At the transmitting frequency, L1 is tuned with C1 (mainly) so the impedance to the desired frequency is quite high.
It will not work very cleanly with an NPN due to the high Ib current spike when the base voltage resonates with a large negative AC voltage resonance with the emitter C load . This positive peak causes Ib to spike with large current this distorts the emitter sine voltage with a small step. You can illustrate that by tuning Rb to low values. However inserting a large base resistor makes this perform better as well as the JFET. It needs a spike current to get started otherwise it may not start to oscillate.
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The JFET runs easily and conducts on the positive cycle with Vgs=0 and continues to ring with Vgs being pinched off. (-ve) With this typical JFET 1K was about optimum for the source in Pavg output , while raising the Rs increases the voltage to swing up to the supply.
It almost resonated at 100 MHz perfectly so I tuned one cap to 100 MHz that was 47 pF to 54.8 pF. With a load of 1k and the inductor at 62.8 ohms at 100 MHz the impedance ratio yields a high Q.
Gate 1Meg has no effect since X_L(f) = 2pi f L = 6.28 * 1e8 * 1e-7 = 62.8 ohms
Check Idss of FET determines Vgs bias
In my simulation, with V^2/Rs the maximal RMS V or average power over any integer N cycles turned out to be between 1k and 1.2 k. This controls the load resistance thus the parallel quality ratio Qp = R/X(f) . This Q ratio is the same as the power ratio on the LC pi network where the caps |Xc|=XL.
This works well for small inductor capacitors with low impedance.
Tuning for 100 MHz can be trimmed within 10% using < 10pF trimmer in parallel with an NP0 = C0G, 47 pF Cap.
This circuit is not enough to be useful and needs a buffer as the FET source not only tunes the frequency but the amplitude with bias current. A 10 pF probe capacitance will lower the around 10% frequency so the source R is a poor output for measurement.
There are several ways to buffer this.
A simple NPN emitter follower works.
Then any probe load C=10 pf is reduced to on the source R by hFE.
But since the swing resonates slightly below 0V, I will pull it up slightly then byapss the series R to eliminate the AC loss.
Now this is not the best buffer, just a simple single supply one. If you wanted 0Vdc, the inductor to ground has the oscillator peaking to Vdd and then ringing to the same below ground and is low impedance, so if you had a +/-Vdd supply you could get twice the 100 MHz amplitude and closer to 0Vdc.
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