how to Design a counter which counts 0, 4, 8, 2, 6

Eng Ali · Dec 23, 2011

Palbert said:
Just out of curiosity, have you done state machine design much in your class?

thanks for help and about your question i think what we done in the class not enough

Eng Ali · Dec 23, 2011

this is the k-map for the three flip-flops

ljcox · Dec 23, 2011

The JK Map is almost right, well done.

You made a mistake with JD.

Also, you only need 3 Flip Flops. A is just connected to Gnd.

In the attachments you will see that I divided the figures by 2 before drawing the Next State Table & the K maps.

I'll look at the T case later, I have other things to do at the moment.

ljcox · Dec 23, 2011

I have looked at the T & D cases.

You have made some minor errors, see the attachments.

However, check what I have done, I can make mistakes also.

EDIT
Fixed the error in the third attachment.

Eng Ali · Dec 24, 2011

i fixed the mistakes

and this is the final results for K-map

now i will start design the first counter and when i finish it i will post it here

ljcox · Dec 24, 2011

Your attachment looks good.

The only comment I would make is that you still have A in the Karnaugh Maps.

You don't need a Flip Flop for A.

It is 8:21 pm here now, so I'll have a look at your counters in the morning.

Eng Ali · Dec 24, 2011

ok no problem i will wait until the morning

i done the counters but i think there is some mistakes

ljcox · Dec 24, 2011

I only found one minor error in the JK drawing.

See attachment.

Eng Ali · Dec 24, 2011

thank you very much

i fix it

now, i want you to help me with the second part
2. Modify your design in question 1.a so that the circuit works according to the following function table
X Y F
0 0 Clear
0 1 No Change
1 0 Parallel Loading
1 1 Count

because i don't have any ideas of the way it done by it

ljcox · Dec 24, 2011

I have attached the data sheet for the 4027 Dual JK Flip Flop IC.

Motorola call it the MC14027, other manufacturers use other prefixes such as CD4027, etc.

Note that the 4027 has Set (S) and Reset (R) inputs. These are called asynschonous inputs since they are independent of the clock. Some manufacturers call them Preset & Clear.

The J & K are called synchronous inputs as they are dependent upon the clock.

Look at the general description, Truth Table & the Block Diagram on page 1.

The Truth Table defines how the FF behaves under the various input stimuli.

You will need gating to control the functions. The inputs will be X & Y.

The outputs of the gating will go to the S & R inputs. You may also have to design some way of preventing synchronous changes when you want to make asynchronous ones.

The first step is to draw Karnaugh maps for the S & R inputs. I suggest you forget about the issue in red above initially until you have seen my next post. It is a side issue at this stage.

I will post another attachment later that will help you understand what you're trying to do.

ljcox · Dec 24, 2011

I could not find a suitable counter data sheet that was relevant to your needs.

So I have drawn the basic block diagram of what you have to do.

I suggest that you concentrate on the Parallel Load & Clear (Reset) functions first.

Then we can think about the Count & No Change functions.

Eng Ali · Dec 25, 2011

I think i have done all the cases except the parallel loads

* I have only 20 hours to finish it and i think it's not enough time

ljcox · Dec 25, 2011

The logic is wrong in your drawing.

Since you are running out of time, I have drawn the Karnaugh maps for the Set & Reset inputs to the Flip Flops and have given you a clue as to how to do the "No change" case.

Eng Ali · Dec 25, 2011

i don't understand the k-maps
and how to do the parallel load

ljcox · Dec 25, 2011

Eng Ali said:
i don't understand the k-maps
and how to do the parallel load

The logic is as follows:-
To Clear all FF, ie. when X = 0 & Y = 0, you apply 1 to all R inputs.

To parallel Load, ie. when X = 1 & Y = 1, you make S = 1 & R = 0 if P = 1 or if P = 0 then you make S = 0 & R = 1.

Where P is the parallel data to be entered.

Eng Ali · Dec 25, 2011

ljcox said:
The logic is as follows:-
To Clear all FF, ie. when X = 0 & Y = 0, you apply 1 to all R inputs.

To parallel Load, ie. when X = 1 & Y = 1, you make S = 1 & R = 0 if P = 1 or if P = 0 then you make S = 0 & R = 1.

Where P is the parallel data to be entered.

where?
we don't learn about parallel load in the class and in the text book it's complicated
so help me please !!!

ljcox · Dec 25, 2011

Parallel Load means that you set the counter according to data applied to the Parallel Inputs.

So, for example, if you applied say 110 to the P inputs, then set X = Y = 1, then the counter would be set to 110.

Then if you set X = 1 & Y = 0, the count will start at 110.

ljcox · Dec 25, 2011

I just did a search for "Electronic counters".

Here is one result.

https://en.wikipedia.org/wiki/Counter

Did you look at the diagram that I attached to my post # 31 ?

Eng Ali · Dec 26, 2011

I finish it and send it to my teacher mybe there are some mistakes .

I just want to say thank you very much for help me without you i never can do it

I grateful to you.

ljcox · Dec 26, 2011

You are most welcome.

It is nice to be appreciated, some people don't bother.

Good luck with your studies.

Please let me know what your teacher's comments were on the assignment.

how to Design a counter which counts 0, 4, 8, 2, 6

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