if .....?.....

[williB]

hmm
what do you use as ground in this circuit?
I have added a Reference point for the coils , which is sort of a center tap on a transformer....

 

[Oznog]

What on earth is that circuit doing?

What's the point of having a "reference" center tap?

Most likely you would use 2 NMOS and 2 PMOS transistors. They will probably need to be "logic level". They will need have the source and drain swapped from how you might normally connect them since the body diode will otherwise conduct at the wrong time. Since MOSFETs are symmetrical and drain/source are the same thing except for the body diode, it should operate fine in this mode.

You'd then want 2 or 4 comparators to drive them, and 1 voltage divider per comparator for a reference. I'd be careful about driving an NMOS/PMOS pair off one output, there's a big overlap in the middle where both transistors will be on and it shorts out the generator.

 

[Oznog]

You know, another thought here. Your FWB will do no charging until its voltage exceeds cap voltage, meaning the duty cycle of the generator gets fairly low.

Now if you employ a boost or buck-boost converter on the input, it will be able to take advantage of the entire waveform. I'm not sure what all this gets you, it's not going to make energy that wasn't cranked in, but I'm pretty sure it will make the generating motor's current capacity greater. This may be important since the motor's size will likely be an issue.

See, those permanent magnet motors are kinda tricky. The output voltage is proportional to speed. So cranking it below a certain speed will not charge anything, but cranking too fast may make an excessive load. You don't want a Vout of 15v to charge a 5v supercap.

Actually if you're using a permanent magnet motor, why not just use a DC motor? Then you will only need a single diode or MOSFET to keep the capacitor from running the motor.

Another thought- caps are nice in that the charge state is immediately and unambiguously apparent by looking at the voltage. So you can build a very accurate "fuel gauge" onto it.

 

[williB]

well i tried my design on the simulator ,
i used all N-channel Mosfets..
i would like to post the simulation so anyone could run it , how could i do that..??
EDIT this is the newist version, its a work in progress.
Ic3 & IV2 add up to almost 7A as seen by IR1..

 

[Oznog]

well i tried my design on the simulator , and it works beautifully..
i used all N-channel Mosfets..

So get rid of M2, M4, M5, and M8. They serve no purpose at all and mess with your ability to switch. That is, they're cascading. Consider M3 and M4 turning on. M3 immediately has a vgs but perhaps not M4. The drain voltage of M3 has to go down before M4 will switch on. And again I don't see where it serves any use.

What you're going to find is it's impractical to use NMOS on the positive side, because you need a driving voltage of V4+vgs to turn it on. You'd have to build a voltage booster or get a driver chip and it's just not necessary when a PMOS will do the job well enough.

Or, copied from your other thread (we're really in a case of duplicate threads here):


What are you using for sim?

 

[williB]

well i just couldnt get yours to work..
as much as i tried , when i would turn on one side the other would short it out..causing the output current to be a few milli Amps at best..
i'm using
Linear tecnology Ltspice Switcher CAD III

 

[Oznog]

well i just couldnt get yours to work..
as much as i tried , when i would turn on one side the other would short it out..causing the output current to be a few milli Amps at best..
i'm using
Linear tecnology Ltspice Switcher CAD III

You made a mistake in your driving signals. Say the coil's positive on top the way it's drawn. You want N1 gate to be high and P2 gate to be low, both on. N2 gate is low and P1 gate is high, both off. N2's and P1's body diodes are both reverse biased and thus off.

It is tempting to tie N1's gate to P1's gate, but this is not acceptable because there's a window that every transition must pass through where both transistors will be on at the same time, shorting out the cap. The same problem can exist in any of these bridge circuits including the others mentioned before.

 

[williB]

In your circuit, I've given each transistor its own control voltage , still dont work..

 

[Oznog]

In your circuit, I've given each transistor its own control voltage , still dont work..

Can you run the scenario I mentioned in the DC sense? I'd like to know which transistor is shorting this out. Or if you could forward the info you're giving the signals. I suspect you must have made some mistake on the driving signals or the transistor model is flawed (unlikely).

 

[williB]

if i could transfer the whole simulation , i would..??

 

[williB]

this is a screen shot of the simulation..
V5 is the "generator" running 20V at 100 Hz with a resistamce of 1.3 ohms ..
V1 , 2,3,4 are the driver voltages..
M1 & M2 are p-channel mosfets
M3 & M4 are N-channel
R1 is a 1.3 ohm load...
but it dont work,

 

[Oznog]

this is a screen shot of the simulation..
but it dont work,

Your PULSE drivers are all mixed. At t=0, SINE starts going positive so M3 and M2 should be on and M1 and M4 off. You're turning on M4 and M2 which is a dead short, then turn on M1 and M3 which is another dead short.

The PMOS gate signal is OFF=VR1 and ON=0v versus ground. You're stating 0v to -12v vs ground, which leaves both PMOS locked in an ON state. So that's another reason it's a dead short.

The width should be 5m- 2*1u at most. The delays are incorrect as well in that they cause overlap. Note that "rise time" in a (0 -12) pulse is in fact the fall time, so it may be more understandable to say the gate pulse for the PMOS is from a high voltage to low. The total pulse width is the sixth field + rise time + fall time so it will stay on longer than it should.
DT=Dead time=2u
TT=Transition Time=1u
M3 PULSE( 0 12 DT TT TT 5m-2*TT-2*DT 10m)
M2 PULSE( 12 0 DT TT TT 5m-2*TT-2*DT 10m)
M4 PULSE( 0 12 5m+DT TT TT 5m-2*TT-2*DT 10m)
M1 PULSE( 12 0 5m+DT TT TT 5m-2*TT-2*DT 10m)

Then you're good to go!

 

[williB]

I read your info , and i'm working on it..

 

[williB]

I'll be damned.. it works..
thank you

 

[Oznog]

Consider this driver for one of the two legs. When the NMOS has a negative Vds, the amp turns on the NMOS gate.

Here's the thing here. Look at the previous circuit and your fixed drivers. OK, when the generator voltage is +1v, do you WANT to turn on the MOSFET pair to connect it to the 5v rail? No, because the 5V will drive the generator like a motor because MOSFETs, unlike diodes, are bidirectional!

You want to turn on the MOSFET only when the generator voltage is greater than the battery voltage. This driver will do that by turning on the transistor only when its voltage is in a particular direction.

This will also avoid all issues with short circuiting the leg. There is a wide span where the generator voltage is not above +5v nor below -5v so neither side will be turned on.

In truth, this circuit is flawed. Many op-amps do not have rail-to-rail inputs and outputs. If the output capability's dropout between the higest output it can give and Vdd is less than Vth of the PMOS, you're good. Now the problem here is the inputs are in fact a few mV beyond the rails and very few op amps handle beyond the rails. Hopefully this will still be tolerable, but I'm just not sure what any given part would do.

Next flaw, the gain may be too high and oscillation is possible so some feedback may be necessary.

Now what's "V+" and "V-"? Well, due to inherent offset errors in the amps, the V+ cannot be 5v. If the op amp has a 4mV offset error, the V+ needs to be like 5.05v and the V- is -0.05v. Otherwise the op amp could turn the NMOS on hard, Vds=1mV, then the generator voltage drops below 5v and it needs to turn off to avoid feeding power back into the gen or worse stay on when the gen voltage is reversed. Well, with a 4mV offset error a 1mV differential signal will be read as 3mV and amplified 10,000 so the output to the gate remains at the +5v rail and the state will never be released, it's a latch. With a -0.05 Vref- and proper gain to prevent oscillation, the Vds will go no lower than -0.05 and once it biases the other way the amp will be able to read it and turn off the transistor.

 

[Oznog]

Now another thought (I've had that circuit in mind for my own similar reasons, I'm seeing so much after having to look through it).

The comparators are only necessary for either the PMOS on the NMOS sides. The other side can be a simple polarity detection on the source. Since amps are hard to find with input and output properties that include V+, that may come in handy. And you don't need to come up with a way to generate both a positive and negative voltage reference.

You'd turn on the PMOS any time between zero crossing and forward conduction. That alone won't cause current to flow. The comparator will turn on the NMOS and let current flow when V5 is greater than VR1+.

In this case the turn-on and turn-off speed of the PMOS can be quite slow which helps the driving requirements. As long as it turns on before the NMOS turns on and turns off before the other PMOS turns on you're fine. An optoisolator could do the job.

 

[williB]

this is from the data sheets for the devices

posted for reference..

 

[Oznog]

Those probably aren't what you're looking for:
1. PMOS rds(min) way, way too large. For PMOS, at 0.45 ohms you'd get lower voltage dropout with a silicon diode or schottky.
2. No reason for cases this big. Many better transistors in the SO-8 pkg. Some dual. Your junction should create insignificant heat in switching mode so there's no need for a pkg like this.
3. If your source voltage is low, you need a logic level device. For example, although 5v will exceed the 2v-4v threshold, the gate voltage may still not be high enough to get the rds anywhere near rds(min). It may not even be enough to overdrive the transistor into the switching mode.

Look up these:
FDS6680 N
IRF7416 P (rds=0.02ohm, vth=-1v)
IRF7309 dual N/P
IRF7303 dual N/N

BTW, SO-8 single transistors is not hard to mount on experimenter's board. Just caddy-corner it on the backside so the gate solders to one pad and some of the drain and source pins solder to other pads. It's good but not essential to attach all the source & drain pins. Unfortunately this does not work with duals since the different pins are located close together,

 

[williB]

I know , i was just using them for reference..

Look up these:
FDS6680 N
IRF7416 P (rds=0.02ohm, vth=-1v)
IRF7309 dual N/P
IRF7303 dual N/N

i 'll check those out..

 

[williB]

I looked up the first one ,, Wow really low on resistance..