Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Inverting Op Amp

Status
Not open for further replies.
The 3rd opamp inverts and the input is positive then the output is trying to go negative, but it cannot go negative without a negative supply, so the output goes as low as it can which is 0V.

Didn't your professor teach you anything about this old circuit?
 
As AG said in post #21, the 3rd opamp is wired to invert the signal.

But the fix is easy. Swap the wires from the first two opamps and the input to the third.
- U1 should feed the non-inverting input of U3 through R7.
- U2 should feed the inverting input through R6.

Why do you have such a large resistance for R10? It's 3.3 Meg resistance into C1, will make a delay between an input change and the output voltage change. The delay will be significantly longer than the 100uS in your notes. It may also add a large measurement error in whatever is monitoring V_out.
 
I've tried replacing 741's with ADA4505 and tying negative supply to ground. Output voltage seems to be 0.
You'll need to only use 0V for the negative power pin. All "ground" connections should be connected to a virtual ground that is half-voltage of your power supply.
 
As AG said in post #21, the 3rd opamp is wired to invert the signal.

But the fix is easy. Swap the wires from the first two opamps and the input to the third.
- U1 should feed the non-inverting input of U3 through R7.
- U2 should feed the inverting input through R6.

Why do you have such a large resistance for R10? It's 3.3 Meg resistance into C1, will make a delay between an input change and the output voltage change. The delay will be significantly longer than the 100uS in your notes. It may also add a large measurement error in whatever is monitoring V_out.
Believe it is a low pass filter for .5 Hz
 
As AG said in post #21, the 3rd opamp is wired to invert the signal.

But the fix is easy. Swap the wires from the first two opamps and the input to the third.
- U1 should feed the non-inverting input of U3 through R7.
- U2 should feed the inverting input through R6.

So you rely on the fact the U3 non-inverting input voltage is always higher than the inverting voltage? But still а dual supply would be preferable because (for some reason?) the bridge is powered only by 1/7 of the supply voltage... and the input voltages of the op-amp followers would be too close to the negative rail.

Why do you have such a large resistance for R10? It's 3.3 Meg resistance into C1, will make a delay between an input change and the output voltage change. The delay will be significantly longer than the 100uS in your notes. It may also add a large measurement error in whatever is monitoring V_out.

Maybe C1 can be connected in parallel to R8? Then the U3 output impedance will remain low.

BTW the resistances R6-R9 are too high for the 741 big input currents.
 
Status
Not open for further replies.

Latest threads

New Articles From Microcontroller Tips

Back
Top