wuchy143
Member
Hi All,
I"m trying to figure out exactly what a latch is in verilog. The code below I have been trying to wrap my mind around but am confused. The way I understand it is that whenever b or c changes it checks to see if b is high and if it is it sets a=c. What's wrong with that????
Example below is from this VERILOG FAQ TECHNICAL
Bad Code
Latch)
1 always @ (b or c)
2 begin
3 if (b) begin
4 a = c;
5 end
6 end
You could download file latch_bad.v here
In the code above, value of a is retained, and it gets changed only when b is set to '1'. This results in a latch. (Need to phrase it right)
Good Code #1
No latch)
1 always @ (b or c)
2 begin
3 a = 0;
4 if (b) begin
5 a = c;
6 end
7 end
I"m trying to figure out exactly what a latch is in verilog. The code below I have been trying to wrap my mind around but am confused. The way I understand it is that whenever b or c changes it checks to see if b is high and if it is it sets a=c. What's wrong with that????
Example below is from this VERILOG FAQ TECHNICAL
Bad Code
1 always @ (b or c)
2 begin
3 if (b) begin
4 a = c;
5 end
6 end
You could download file latch_bad.v here
In the code above, value of a is retained, and it gets changed only when b is set to '1'. This results in a latch. (Need to phrase it right)
Good Code #1
1 always @ (b or c)
2 begin
3 a = 0;
4 if (b) begin
5 a = c;
6 end
7 end