Latch LS374 works for sometimes and doesn't work at all next clocks

[ahmedragia21]

I'm trying to interaface with an 8080bus, that's the schematic of the socket of it:
I'm latching all of the signals, A1,CS1,CS2, IOWR as clock to LS374, and the databus.
Here is the schematic of the board that has the two latches connected

I'm powering the latches from STM32F429I Discovery board, 5V, GND. The ground of the Device 8080 is connected to STM32Board and to the PCB of the two latches.
I captured the data using logic analyzer, here is the data:
MPC LATCH IOWR
6E 30 1
7E 30 1
7A 30 1
21 30 0
21 30 1
21 21 1 <--- latch is valid here
7F 21 1
7E 21 1
7F 21 1
7A 21 1
6A 21 1
7A 21 1
71 21 1
61 21 1
66 21 1
76 21 1
7A 21 1
6A 21 1
7A 21 1
78 21 1
68 21 1
60 21 1
70 21 1
76 21 1
7F 21 1
6F 21 1
60 21 1
7F 21 1
6F 21 1
61 21 1
7D 21 1
6E 21 1
78 21 1
7F 21 1
6F 21 1
6A 21 1
7A 21 1
71 21 1
61 21 1
68 21 1
78 21 1
74 21 1
24 21 1
21 21 1
6F 21 1
62 21 1
72 21 1
7A 21 1
79 21 1
69 21 1
63 21 1
7F 21 1
78 21 1
79 21 1
69 21 1
6E 21 1
67 21 1
77 21 1
7D 21 1
6D 21 1
6F 21 1
7F 21 1
76 21 1
66 21 1
60 21 1
70 21 1
78 21 1
7A 21 1
6A 21 1
61 21 1
70 21 1
73 21 1
3E 21 0
3E 3E 1 <--- latch is valid here
7F 3E 1
70 3E 1
7E 3E 1
6F 3E 1
60 3E 1
70 3E 1
78 3E 1
68 3E 1
60 3E 1
70 3E 1
77 3E 1
67 3E 1
6F 3E 1
7F 3E 1
70 3E 1
75 3E 1
65 3E 1
6E 3E 1
7E 3E 1
7A 3A 1 <--- latch is corrupted here
20 12 1 <--- latch is corrupted here
20 3A 0 <--- latch is corrupted here
20 20 1
7F 20 1
75 20 1
65 20 1
6F 20 1
7F 20 1
77 20 1
67 20 1
69 20 1
79 20 1
7F 20 1
6F 20 1
7F 20 1
70 20 1
68 20 1
78 20 1

I have no idea what's going wrong, and why the latch works for few moments and then is corrupted.

 

[ahmedragia21]

Picture from the system

 

[Papabravo]

would that inverter work ?

https://www.ti.com/lit/ds/symlink/cd4010b.pdf?ts=1722598160395&ref_url=https%253A%252F%252Fwww.google.com%252F

How do I connect it please ?

You don't need six of them. A single inverter in a small package should suffice. Something like:

https://www.ti.com/lit/ds/symlink/sn74lvc1g04.pdf?ts=1722583138591

or similar should work.

 

[ahmedragia21]

Can I know what is this connector ?

 

[rjenkinsgb]

Are you trying to capture just the data to the LCD, or every peripheral (I/O) write made by the CPU to any device??

If it's only the LCD, the CPU data sheet is irrelevant. And you need the gating I described to limit the volume of data collected.

If the entire CPU, you need more address lines so you know what's happening - and probably a hardware FIFO to allows the monitoring CPU to have a chance of keeping up without any overruns.

 

[Tony Stewart]

But googling generally speaking D F-Fs can be used as "latches". Looks like we need
"latch" def police to get busy .

'74 ICs are both FF's and latches with RS inputs. So it is contextual.
We don't need another she/him debate or even an ID tag..
Yawn.

 

[ahmedragia21]

rjenkinsgb
Thanks, I want to capture only LCD.
Would someone please tell me with the pitch measurment and which ffc socket should I use