A latch in Verilog is exactly the same as a latch in electronics ( Think R-S latch ) Latches are generally bad because they are usually products of poor coding. In your examples above, the intent is to create a combinatorial function described by:
a = b AND c.
However, in the first example, the code erroniously creates a latch, due to poor coding method. In that example, a will receive c when b is high, but will retain the value of c after b is deasserted. That isn't what the code was intended to do (typically)
There are few reasons to create latches, but the assumption is that whenever a value needs to be saved, one should use a clocked element (flip-flop) and so latches should be avoided.