Latch In Verilog

Hi All,

I"m trying to figure out exactly what a latch is in verilog. The code below I have been trying to wrap my mind around but am confused. The way I understand it is that whenever b or c changes it checks to see if b is high and if it is it sets a=c. What's wrong with that????

Example below is from this VERILOG FAQ TECHNICAL

Bad CodeLatch)
1 always @ (b or c)
2 begin
3 if (b) begin
4 a = c;
5 end
6 end
You could download file latch_bad.v here

In the code above, value of a is retained, and it gets changed only when b is set to '1'. This results in a latch. (Need to phrase it right)



Good Code #1No latch)
1 always @ (b or c)
2 begin
3 a = 0;
4 if (b) begin
5 a = c;
6 end
7 end

A latch in Verilog is exactly the same as a latch in electronics ( Think R-S latch ) Latches are generally bad because they are usually products of poor coding. In your examples above, the intent is to create a combinatorial function described by:

a = b AND c.

However, in the first example, the code erroniously creates a latch, due to poor coding method. In that example, a will receive c when b is high, but will retain the value of c after b is deasserted. That isn't what the code was intended to do (typically)

There are few reasons to create latches, but the assumption is that whenever a value needs to be saved, one should use a clocked element (flip-flop) and so latches should be avoided.

hey brownout! Thanks. Makes sense.