Latch LS374 works for sometimes and doesn't work at all next clocks

[ahmedragia21]

I'm trying to interaface with an 8080bus, that's the schematic of the socket of it:
I'm latching all of the signals, A1,CS1,CS2, IOWR as clock to LS374, and the databus.
Here is the schematic of the board that has the two latches connected

I'm powering the latches from STM32F429I Discovery board, 5V, GND. The ground of the Device 8080 is connected to STM32Board and to the PCB of the two latches.
I captured the data using logic analyzer, here is the data:
MPC LATCH IOWR
6E 30 1
7E 30 1
7A 30 1
21 30 0
21 30 1
21 21 1 <--- latch is valid here
7F 21 1
7E 21 1
7F 21 1
7A 21 1
6A 21 1
7A 21 1
71 21 1
61 21 1
66 21 1
76 21 1
7A 21 1
6A 21 1
7A 21 1
78 21 1
68 21 1
60 21 1
70 21 1
76 21 1
7F 21 1
6F 21 1
60 21 1
7F 21 1
6F 21 1
61 21 1
7D 21 1
6E 21 1
78 21 1
7F 21 1
6F 21 1
6A 21 1
7A 21 1
71 21 1
61 21 1
68 21 1
78 21 1
74 21 1
24 21 1
21 21 1
6F 21 1
62 21 1
72 21 1
7A 21 1
79 21 1
69 21 1
63 21 1
7F 21 1
78 21 1
79 21 1
69 21 1
6E 21 1
67 21 1
77 21 1
7D 21 1
6D 21 1
6F 21 1
7F 21 1
76 21 1
66 21 1
60 21 1
70 21 1
78 21 1
7A 21 1
6A 21 1
61 21 1
70 21 1
73 21 1
3E 21 0
3E 3E 1 <--- latch is valid here
7F 3E 1
70 3E 1
7E 3E 1
6F 3E 1
60 3E 1
70 3E 1
78 3E 1
68 3E 1
60 3E 1
70 3E 1
77 3E 1
67 3E 1
6F 3E 1
7F 3E 1
70 3E 1
75 3E 1
65 3E 1
6E 3E 1
7E 3E 1
7A 3A 1 <--- latch is corrupted here
20 12 1 <--- latch is corrupted here
20 3A 0 <--- latch is corrupted here
20 20 1
7F 20 1
75 20 1
65 20 1
6F 20 1
7F 20 1
77 20 1
67 20 1
69 20 1
79 20 1
7F 20 1
6F 20 1
7F 20 1
70 20 1
68 20 1
78 20 1

I have no idea what's going wrong, and why the latch works for few moments and then is corrupted.

 

[aliarifat794]

From the provided logic level analyzer data, the latch appears to work initially but then becomes corrupted. If possible, use an oscilloscope to check the timing of the control signals and the data bus relative to the latch enable signal (IOWR).

 

[danadak]

What power rail bypassing are you using for each logic part and type
of capacitor ?

If you have a DSO place it on infinite persistence, and monitor a power rail
to see what pk-pk noise looks like.

Regards, Dana.

 

[ahmedragia21]

danadak
I'm not using nay bypassing. I don't have DSO

 

[danadak]

No bypassing fast logic = disaster.

 

[ahmedragia21]

danadak
Which cap should I put and how much ?

 

[danadak]

As close as possible to power pins of LS374, a .01 and .1 uF ceramic disk.

Show a picture of your prototype boards/layout. Well focused and post it.


Regards, Dana.

 

[ahmedragia21]

danadak

 

[danadak]

Is there a ground plane in that layout ? Where one leg of caps tied close to power
pins of logic, the other into the ground plane ?

See attached doc on layout.

 

[rjenkinsgb]

This has already been asked and answered, here:

Using latches to capture 8086 bus

I'm trying to capture the data using stm32, I have used two latches as the following diagram and this is the schematic of the bus for your reference I'm not getting any LCD commands that was referenced in the answer, I only get two LCD Commands 0x60, and CS1,CS2 = 1, A1 = 0 or 1, and they are...

www.electro-tech-online.com

As shown you are trying to capture every I/O write cycle from the MCU, rather than only ones relating to the LCD data bus.

 

[ahmedragia21]

rjenkinsgb
I'm filtering that in software, why do I need logic gates ?