LINEAR VOLTAGE STABILIZER

sxy said:

Thanks a lot!
VL=A(Vz-Vi)
VL-is the output of the circuit
Whereas Vi is the input of the negative side of the op-amp.
But you assumed that VL and Vi is the same thing
and it is not correct.
IL*RL=VL is the output of the circuit
Thanks

Click to expand...

That is incorrect. VL=Vz as long as Series transistor does not overheat.

Also there is no error due to Vbe as that is reduced by 10^5 from 600 mV to 6 uV.

If VL-Vz= small error And Vz can be made stable with large R or a current source or large R + PTC to compensate for Zener temperature coefficient.

VL= Vio + Vz , while Vio is nearly 0. Where Zener has a rated If of 5mA and rated Vz with Zzf or series Rs that depends on voltage and power rating of Zener. nominal << 50 Ohms for low V.

So with an attenuation of Vin due to Rs/(Rs+R) that depends on current and Vin for choice of R. So if Vin =12V Vout =3.3 for 3 to 5 mA, R= 7.3V/5mA ~ 1 kohm compared to 25 ohm nom or an LED at 30 mA would have Rs= 12 ohms thus the PSRR = 25 ohm/ 1k or more than 30 to 40 dB attenuation.

With a current source and PTC the PSRR could be 60 dB and with a Band Gap Reference Diode even better. This is similar to any LDO design with 10mV line regulator for a 25 V input range.

The output of the OpAmp is A( V+ - V-) = A(Vz - Vl)

Vi = V+ - V- = Vz - Vl
The output of the OpAmp = A x Vi = A x (Vz - Vl)

Note I am ignoring the Vbe of the transistor (its inside loop, so winds up
being divided by A).


Regards, Dana.

danadak said:

The output of the OpAmp is A( V+ - V-) = A(Vz - Vl)

Vi = V+ - V- = Vz - Vl
The output of the OpAmp = A x Vi = A x (Vz - Vl)

Note I am ignoring the Vbe of the transistor (its inside loop, so winds up
being divided by A).


Regards, Dana.

Click to expand...

Vo=A x Vi is wrong. That is the error Voltage.

The inverting gain is zero and the non-inverting gain is 1+0. So Output = Vz. We can neglect input offsets and Vbe as well.

This is true :



Vo = A(Vp - Vn) = A( Vz - Vl) for circuit OP posted.

Where A = Aol inside OpAmp = very large.

Ignoring all other minor errors for the circuit.


Regards, Dana.

danadak said:

This is true :

View attachment 138584

Vo = A(Vp - Vn) = A( Vz - Vl) for circuit OP posted.

Where A = Aol inside OpAmp = very large.

Ignoring all other minor errors for the circuit.


Regards, Dana.

Click to expand...

OK Dana but that is not the closed circuit in question. That is just a high gain error amplifier or ideal Op Amp. The answer to the initial question is simply. Vout = Vz The error amplifier nulls the output error with 0 differential input and when unity gain that error is neglible.

Tony Stewart said:

OK Dana but that is not the closed circuit in question. That is just a high gain error amplifier or ideal Op Amp. The answer to the initial question is simply. Vout = Vz The error amplifier nulls the output error with 0 differential input and when unity gain that error is neglible.

Click to expand...

Yes that is the result when 100% feedback is applied, or very high levels,
like 10 to 100%. But if we fdbk .1%, .01% then the loop G drops like a
stone and all that benefit of internal G starts disappearing. Here is an
example of that applied to CM analysis :



The use of the "ideal" model is to replace the OpAmp in the circuit
with that model, then write the loop and node equations, and taking the
final equation when Aol approaches infinity, and as you say the errors
drop out. If we had set the external G real high with tiny fractional fdbk
to the OpAmp, then those errors become way more significant.

All this just a part of Classic OpAmp analysis.


Regards, Dana.

No need to complicate this. It's an LDO design like this 8A LDO. Here like the LM317 adjustable with a floating ground and external bias resistors to choose a 1.24 V drop from OUT to ADJ so as to boost the OUTPUT.

No need to complicate this.

Click to expand...

Exactly, thats why the simple model was used. Tha MATLAB was only pointed at our discussion
about use of the simple model. As its simple itself.


Regards, Dana.

Tony Stewart said:

No need to complicate this. It's an LDO design like this 8A LDO. Here like the LM317 adjustable with a floating ground and external bias resistors to choose a 1.24 V drop from OUT to ADJ so as to boost the OUTPUT.

View attachment 138591

Click to expand...

This doesn't look like an LDO regulator?, using an NPN transistor for the series element gives too much voltage loss - mind you, the diagram also shows the output connected directly to the substrate (ground?). Datasheets often seem to have errors.

Yes its an LDO, here an ON part (but obsolete) with same architecture -


The connection to substrate is the collector....LM1084 ?




Regards, Dana.

danadak said:

Yes its an LDO, here an ON part (but obsolete) with same architecture -

https://www.onsemi.com/pdf/datasheet/cs5210-1-d.pdf

Click to expand...

Not as I'd accept as particularly LDO - that datasheet suggests a drop out of about 1 volt - I'd want about a tenth of that for LDO.

LDO's usually output from the collector of the series transistor, so as to avoid the excessive voltage drop caused by the Vbe voltage.

Its dropout at 10 A is 1.4V max, 1.15V @ 4A. What part do you know does .1 V at 10 A, or 4A ?

Then there is the loss definition of what constitutes an LDO, no real industry standard....?
Although manufacturers seem to settle on marketing definition of 1 V......even thou specs
in their datasheets may be something else.

LDOs also available with MOSFET pass element.


Regards, Dana.

All classic BJT LDOs have a 1.5V drop near rated current. Nigel refers to a FET-based LDO rated for xx mv to 1V drop. typ. Remember Low in LDO was relative to 1975 and with the advent of enhanced MOSFETS, they can be a very low dropout.

The schematic I posted is the current boosted much better version than the LM317. They all use Darlingtons and this question is an exception. But the Op Amp has headroom as well and has a Darlington so they are essentially the same. There are tricks to design Darlingtons with superbeta transistors to reduce saturation voltage,