Linear vs Saturated region operation of switch in converter

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dave_dj88

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Hey,

I cannot understand how there is higher efficiency if a transistor switch is operated in the saturated mode (ON) rather than in the linear region in a power converter when the current in the saturation region is higher. Doesn't this make it less efficient?
(2nd year EEE student)
Thanks,

David
 
Simple maths, W = V x I

If I = zero, then W = zero as well (transistor turned OFF), If V = zero, then W = zero (transistor turned fully ON).

In practice the transistor voltage won't be zero when it's fully turned ON, but it will be very low, meaning W will be very low.

The most dissipation will occur during changing states, particularly going from ON to OFF, where special measures are used to make it as quick as possible.
 
In a converter you want the transistor to operate as a switch, either fully on or off. When on, the current is ideally determined by the rest of the circuit, not the transistor. In the linear region the transistor dissipates power, which would obviously reduce efficiency, so you want the transistor to switch as fast as possible to spend a minimum of time in the linear region.
 
I think you are confusing power dissipation with efficiecy. When current increases the power dissipated will increase (probably for most devices with constant voltage drops or resistances), but so will the power that is being passed through the switch to the load. If the power being passed to the load increases faster than the power being dissipated, the efficiency increases. So a partially on switch passing 100A might be dissipating 100W and be passing 900W through it to the load. If you "turn the switch on more" so it has a lower voltage drop and passes more current to the load, it may be passing 200A and be dissipating 150W, but if 2000W are now getting to the load, your switch efficiency has just increased even though power dissipated has increased. So the absolute power being lost might increase, the amount of power relative to power of the load might decrease (thus increasing efficiency).

Think of a resistor. When you reduce the resistance, the power dissipated goes up. You're reducing the resistance so the losses should go down...shouldn't it? Well when you reduce the resistance, the current goes up by the square of that so the current increases faster than the resistance increases.

For a MOSFET, think of power being the area inside a rectangle/square and current being the length of one side of the square and voltage drop across the switch being the other side. When the switch is on you have a very large current but a very small voltage drop the area of the power rectangle is very thin and has almost no area. THe same thing happens when the switch is off and you have a very high voltage drop but no current. But when you have half-way of maximum current and half-way of maximum voltage drop you get a squarish rectangle with a very large area even when the current and voltage drop sides of the rectangle are shorter than the previous two scenarios.
 
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Thanks

Thanks all!

I'll be doing a project called "Maximum Power Point Solar PV Tracker employing Supercapacitor Bank" for my final year project.and needing to brush up on some theory.

Cheers all!
 
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