Logic circuit for two cameras and one flash.

[Hermit]

I am trying to design a simple logic circuit to combine the flash pulse from two cameras to trigger one of the camera's flash units for stereo photography. I've been using a PIC up to this point, but the logic seems so simple, using a PIC seems over kill (and too expensive).

Each camera produces a short pre-flash test pulse, reads the test image, calculates the main flash pulse needed, then takes an exposure with the main full flash pulse. The intensity of the flash pop depends on the length of the flash pulse. The camera produces the main flash pulse at the beginning of the exposure, so I use the second main flash pulse of the two cameras so that when the camera shutters are out of sync, the flash pop appears on both exposures.

Anyway, I've been trying to come up with a simple latch or flip-flop circuit to do the job, but I can't get it.

Here are the flash pulse wave forms. The first two are sample traces from each camera, and the third trace is the one I would like to send to the flash strobe unit, which is simply the later of the two camera traces. The circuit will need to run on 3 volts. Any help would be much appreciated.

 

[Diver300]

A PIC is not overkill, and it would not be too expensive. A pic12F629 would work and they cost less than $1.

You don't need accurate timing, in that the times can be a few percent out without harm, so you can use the internal RC clocks on a PIC, not a crystal oscillator.

You do want the ability to adjust the times and the ability to ignore the pre-flash, and a PIC looks perfect for that. You would need at least half a dozen gates plus timing resistors and capacitors to do it without a PIC.

On the stero photography side, two flashes on the cameras would probably be a mistake. If the cameras aren't perfectly synchronised, the shadows on each photo will look different and the images won't look right when viewed together. I've made that mistake myself.

It can be easier to have very long shutter times, basically working in the dark, if you have cameras that can focus and leave the shutters open. You open the shutters, operate the flash, and close the shutters. Exact timing isn't important and there is only one light source so only one set of shadows.

 

[Hermit]

Thank you for your excellent comments!

Still, I think a PIC has its limitations in this situation. With the internal 4MHz R/C oscillator, the first 20 usec pre-flash trigger pulse happens pretty quickly, within 20 instructions excuted by the PIC. In my experience, this length pulse is difficult to detect consistently while polling two ports at this oscillator speed.

Increasing the oscillator speed should help, but means a external oscillator. The maximum recommended oscillator speed at VCC of 3 volts is 10MHz, which gives about 50 instructions during this same flash pulse--better, but still barely enough to measure two of these pulse lengths.

The 16F629 has the ability to generate an interrupt on change of a port, but in my experience, the extra overhead of the interrupt keeps it from helping much.

Anyway, so I was hoping to cut across these limitations with a couple of very fast gates and/or latches. After spending many hours with the logic and coming up with little, I am sort of happy to hear that it is also a difficult solution.

 

[ljcox]

As I understand it, either camera A or Camera B will be the first to flash.

Your waveform diagram shows the case where Camera A is first.

So if this is true, then what you need is a JK Flip Flop with the Clk input of one FF (call it FF A) connected to the Cam A signal and the other Clk (ie. the Clk of FF B) to the Cam B signal.

The K inputs would be connected to gnd (assuming the K is active high) and the J input of FF A is connected to the Q bar output of FF B and vice versa.

When the first pulse arrives, the respective FF is set and it prevents the other one from setting when the other pulse arrives.

The Q output of the FF A would be connected to a gate circuit that allows the pulses from Cam B to the output.

And, the Q output of the FF B would be connected to a gate circuit that allows the pulses from Cam A to the output.

So all you need is a NAND gate configured to provide this logic.

In other words, you need 2 ICs, a Dual JK Flip Flop and a Quad NAND gate.

EDITS in red

 

[ljcox]

Hermit,
I made an error in the previous post. I'll edit it now to correct it.

 

[Hermit]

Thank you for your help!

I included a schematic based on your description with some part numbers that seem to match. I used a positive edge triggered JK flip flop with the capability of a low voltage supply. I also included a single OR logic gate to combine the pulses, also low voltage.

Does this circuit need extra parts to do a reset after the last pulse in preparation for the next pair of pulses?

 

[Hermit]

Opps, I missed your edit. Here is an updated schematic to reflect your changes.

I can add an OR gate at the right side to combine the two flash pulses. Actually, leaving them separated suits me better because I need to pipe the result back to the internal flash of each camera, and it would be better to have only one camera flash go off rather than both.

 

[ljcox]

There is one error. The K input is active Low, so it needs to be connected to the +3.3 Volt line (see my comment about K in my first post). CLR and PRE are also active low. So connect PRE to the +3.3 Volt line also.

Tie the 2 CLRs together and connect to the junction of a 3k3 resistor (other end to +3.3 V) and a push button (the Reset button). The other side of the PB goes to Gnd.

You need a 100 nF ceramic capacitor between pins 8 & 16 of the 74HC109 to act as a bypass. It will NOT work properly without this cap.

You can use one of the NAND gates to do the OR function - unless you need them as inverters as drawn.

 

[ljcox]

Opps, I missed your edit. Here is an updated schematic to reflect your changes.

I can add an OR gate at the right side to combine the two flash pulses. Actually, leaving them separated suits me better because I need to pipe the result back to the internal flash of each camera, and it would be better to have only one camera flash go off rather than both. I don't understand this point.

I don't see how you can keep them separate.

I thought the whole point was to output one waveform which is the later of the 2 input waveforms.

To do this, you have to OR the outputs of the NAND gates.

As I said, you can use one of the NAND gates as an OR gate (see attachment). The 4th NAND gate will then be spare and its inputs should be tied to Gnd.

 

[ljcox]

having thought further about your point, I think I now understand it.

For example, if Cam A was to flash first, Flash B would flash when the Cam B input arrives.

 

[Hermit]

Exactly right. Triggering both camera strobes would increase the flash range, but the exposure may not be right.

Here is the updated schematic. Rather than use a reset button, I linked the reset to the shutter button circuit. The shutter circuit just has a pull up resistor, and is grounded when the shutter button is pressed. I needed the MOSFET to reverse the logic of the shutter circuit.

Logic tables for these flip-flops are hard to follow, but this circuit is looking pretty good to me!

 

[ljcox]

What is it about the FF logic tables that you find hard to follow? Let me know and I'll explain.

 

[Hermit]

Seems like there are so many options. How do you know where to begin with a logic problem?

I am also going to try to put together a similar circuit for the outside of a camera. This would use active low generated by the SCR in the camera closing the hotshoe contact. It also would need output active high to run the gate of an SCR as well. I'm thinking the same sort of circuit, but with negative edge triggered FF's, and logic 'or' output using a quad NOR chip. I'll need to use some timing caps and resistors to reset the circuit automatically though.

 

[jankop]

This would use active low generated by the SCR in the camera closing the hotshoe contact.

On Hotshoe is't preflash signal usualy. What are your DIY cameras?

 

[ljcox]

Seems like there are so many options. Do you mean Flip Flop options? If so. there are broadly only 3 types. RS, D type and JK.

How do you know where to begin with a logic problem? See below.

I am also going to try to put together a similar circuit for the outside of a camera. This would use active low generated by the SCR in the camera closing the hotshoe contact. It also would need output active high to run the gate of an SCR as well. I'm thinking the same sort of circuit, but with negative edge triggered FF's, and logic 'or' output using a quad NOR chip. I'll need to use some timing caps and resistors to reset the circuit automatically though.

You start with a description of what you want. This could be verbal or a flow chart or both.

For sequential logic, draw a state transition chart and waveforms.

For combinational logic, I usually start with waveforms and Boolean expressions.

Then decide what inputs and outputs you need and whether they are active high or active low. This determines whether you need NAND or NOR gates or a combination of the two. Sometimes there is some advantage in using an AND or an OR gate package.

One advantage of NAND and NOR gates is that unused ones can be used as inverters.

I don't know if this helps, if not ask more questions.

 

[ljcox]

Hermit,
Here is a circuit I designed for someone in this forum a year or 2 ago.

You may find it helpful in advancing your understanding of sequential logic.

Note that U1 is a -ve edge trigger JK and U2 is a +ve edge trigger D type.

Ignore U2 at first, only study how U1 is configured to act as a Modulo 3 counter. Then look at U2 and how it provides a 50/50 duty cycle.

 

[Hermit]

Len, your comment previously about using a NAND gate as an OR logic is making sense to me now. Here I am using NOR gates as AND logic.

Here is a go at converting the previous flash circuit into a active-low version for cameras with external hotshoes and a external hotshoe flash. I took your advice to step through the logic, in this case starting with the output and working back to the input.

I think the 2M resistors and 0.33uF caps will work to reset the latch function of the flip flops after about 660 msec without a reset button. The hotshoe of the cameras will typically pull the center pin low for at most 120msec, so the reset time out interval should be plenty. The input impedence for the flip flops is quoted on the spec sheet at less than 0.1 uA, so I should be able to get away with the 2M resistors.

By swapping the SCR for a MOSFET for use with modern low voltage flash units, this circuit would use about 15uA, maybe low enough to power it from the flash trigger voltage without a separate battery for the circuit.

 

[jankop]

Haw-haw... !

 

[ljcox]

Very good. You seem to have grasped the ideas.

I notice that both of the AND gates are enabled initially and when a FF is set, it disables the other gate. Whereas in my circuit, both gates were initially disabled. Your method means that the first pulse is sent to the output whereas in my circuit, it was the second pulse.

I assume you prefer it this way.

Another way to do it would be to have both gates disabled initially and when the pulse arrives, enable the relevant gate to pass it through to the output, ie. connect pin 3 of the NOR to pin 6 of the FF (/Q) and pin 8 of the NOR to Q/ of the other FF (pin 7).

 

[Hermit]

Yes, I see you are right! My intention was again to have both gates disabled initially, then a FF would enable the opposite gate to allow the second camera flash pulse to pass. I think the design changes I made will do this. I also switched to the '73 version of the FF since I did not need the Preset pins.

Do you think the FF clock input pins need static protection (resistor and zener)? I can't seem to find information about internal ESD protection for this part.