LTSpice sine wave out of voltage source [solved]

[Mihai1396]

Hello,

I tried to modify my .tran command so it would simulate more quickly a more advanced circuit. Using .tran 0 2m 1u 100n uic on a small design and got this. (click "this" for picture).
Anyone knows why is this happening?

Thank you!

Edit1: Probes placed on the wires that are not connected to anything.

 

[alec_t]

Welcome to ETO!
We're not psychic. Please post your .asc file, using the 'Upload a file' button.

 

[ronsimpson]

We're not psychic.

I was going to say I am psychic, but I don't see what the problem is?
I get the top voltage at +7.5V, the bottom voltage at -7.5V.
Are you looking at node3 on the (+) of the opamp?

 

[MikeMl]

Garbage In, Garbage Out

If you let LTSpice do the work, instead of circumventing its built-in "artificial intelligence", then you will see that the circuit you drew has a stability problem. If had read the Help File, you would have learned that it is a bad idea to force an outcome by using the "uic" directive, because that usually causes un-natural results.

It is better to let LTSpice do an initial conditions solution, either explicitly as a .OP solution, or implicitly as part of a .TRAN solution. .uic specifically screws with that...

Here is the .OP solution. I purposely unbalanced the R1 R2 voltage divider +-1% to show the effect. Note that the opamp really does create a buffered "rail splitter". I labelled the nodes so we can see what is what. Read the Help File about what the .OP sim actually does.



Now, do a .TRAN sim to see what happens in the time domain as the circuit is "released" from the values found in the .OP run, above. Note that the circuit breaks into oscillation because of the attributes of the OP07 (primarily GBW). You can see the behavior after only a few us; you where simulating for thousands of cycles of the oscillation. No wonder it took lots of cpu cycles before finishing the sim. Mine runs in less than 1s.



So, how do you stabilize it? Without doing a detailed analysis, I fall back on experience. Adding bypass cap(s) to either or both rails, which you would see in a "real" application of this circuit does it:

 

[MikeMl]

Interesting that mine oscillated, and Ron's did not. Here are the Spice settings for my sims...

 

[ronsimpson]

Interesting that mine oscillated, and Ron's did not.

My "Max Threads" only allows 1 or 2. I have not updated in 85 days.
I see uV of noise/oscillation but not volts.
Your oscillation is near 1mhz so that is probably at the top end for the amp. I think a capacitor almost anywhere will help.

I made one of these in real life (if there is such a thing). I connected a capacitor from V+ to gnd and from gnd to V-. (audio project and needed a +/- supply with a center point)

 

[MikeMl]

My "Max Threads" only allows 1 or 2...

I am running on a 64bit quad-core processor.

 

[MikeMl]

Lots of good reading on "rail spitters" here.

 

[ronsimpson]

Thanks for the link. I have used the National/TI "rail splitter". Low power but often you only need mAs (long term) and high current short term. So add capacitors.

 

[Mihai1396]

@MikeMI thank you very much for your answer. There was a capacitor on the design I copied but I choose not to include it because I could not understand its purpose.

 

[MikeMl]

@MikeMI thank you very much for your answer. There was a capacitor on the design I copied but I choose not to include it because I could not understand its purpose.

Even with the bypass, the circuit is only marginally stable (on the verge of oscillating, or damped oscillation). A more detailed analysis to prove stability under varying loads is in order. My guess, the OP07 is not the best opamp for this application...