mo' bits mo' problems - daq project conversion and transmission doubts

in other words you need to multiplex two 8 bit values? if you have two 8 bit ADCs at the tx end, you need two 8 bit DACs at the receiving end. the serial clock needs to be 16x the sampling rate in order to send all of the data within a sampling period. the best way to multiplex the data is send the contents of one shift register, and then the contents of the other, and switch between filling one 8 bit register and the other at the receiving end, so you will need to divide the serial clock by 8 and use that signal to select the receiver register. after that, you dump the contents of both shift registers to their DACs (as parallel 8 bit data).

Yes, I was not sure what was the best course of action. Like, how exactly to define the selecting signal for the mux since I gotta have some clock managing beforehand.
I mentioning using mux, because I only have one channel to transmit and one sync channel, but my instructor said probably not the best way, but he's been very cryptic regarding instructions to this project, so I have been doing all sort of redundant models to try and figure out the simplest setup.
However your reply is very close to what I've gathered in other forum. I haven't been able to remodel it, but once I do I'll post updates.
Thank you so much for the help!

I wouldn't do any multiplexing. I'd just run the serial output of the first 8bit shift register into the serial input of the second SR, making a straight 16bit SR. And the same at the receive end, two cascaded 8bit SRs.

The next question is framing. How does the receiver know where the beginning and end are?

I would use a 5 (or more) bit counter and some additional logic at the transmit end to control the timing.

16 clock pulses would be used for transmission, then a silent period greater than or equal to 16 clock pulses.
During this silent period:
- The parallel ADC data is latched into the two sending SRs.
- A missing pulse detector at the receive end indicates that the receive SR has 16 bits of valid data. This data is transferred into two 8bit holding latches.

ChrisP58 said:

I wouldn't do any multiplexing. I'd just run the serial output of the first 8bit shift register into the serial input of the second SR, making a straight 16bit SR. And the same at the receive end, two cascaded 8bit SRs.

Click to expand...

did that, took me a while to get it right because I wasn't very familiar with the pins, but then I had other issues...

ChrisP58 said:

The next question is framing. How does the receiver know where the beginning and end are?

I would use a 5 (or more) bit counter and some additional logic at the transmit end to control the timing.

Click to expand...

namely, my waveforms were all distorted, which makes me believe I'm clocking it too slow or messing it up at some crucial point before that.

shoud I use a timer for that or a counter then a comparator? do both registers in the tx end work at the same clock rate? I believe not, but I'm not sure and right now I'm having trouble to trust my waveform readings.
second question is: how do I compare the output of 8 bit counter bits in multisim 11, where I couldn't find a comparator higher than 8 bits?

https://imgur.com/r5DaQFh
oh, and this is how the frankenstein looks at the moment

icarosfar said:

did that, took me a while to get it right because I wasn't very familiar with the pins, but then I had other issues...

namely, my waveforms were all distorted, which makes me believe I'm clocking it too slow or messing it up at some crucial point before that.

Click to expand...

They're distorted because the digital data feeding your DACs is constantly moving. You need to capture the deserialized data at just the right moment and store it in another register to feed the DAC.

You need a 5-bit counter, but those are rare. The 74HC590 is an 8-bit synchronous counter. Just ignore the upper three bits.

Your oscillator always drives the clock of the counter. Also run the oscillator to an AND gate along with the counter output E. The output of the AND gate is your shift clock of 16 pulses, then a silent period of the same duration. That is the signal that goes to all shift register clock pins, both tx and rx.

The last thing you need to do at the TX end is generate the parallel load signal. I would use a 74HC138 decoder, but you can use a 4-bit comparator. You need to load when shifting is inactive, and that is when counter output E is low. I recommend against loading immediately before shifting starts, so lets have counter output D be low as well. Tie the other two inputs to counter outputs B and C, and compare them to High, though that's arbitrary.

At the receive end you need:
- A missing pulse detector watching the clock signal. I'll let you research this one. Timing target is for it's output to go high about 40 to 80% through the silent period of the clock stream.
- Two cascaded 8-bit serial in, parallel out shift registers. Same clock to both.
- Two 8-bit storage registers. When the missing pulse detector goes active, these take a snapshot of the output of the shift registers.
- Two 8-bit DACs. Tied to the outputs of the storage registers.
Note, the 74HC595 integrates both the shift and storage registers in a single package.